gateware-20230529

On par with reSID

* Keep control registers in sync with waveforms for two SIDs
* Keep within timing budget of 20 FPGA cycles per phi2 cycle

With the notable exception of the filter, this should now be on par with
reSID in VICE.

gateware-20230528

Combined waveforms

* Corrected samples for 6581 pulse + sawtooth
* Zeroing of the 6581 oscillator MSB via combined waveforms
* Corrected zeroing of noise LFSR bits via combined waveforms
* Corrected 8580 waveform 0

gateware-20230507

Corrected envelope counter delay

* Corrected envelope counter delay
* Sample volume closer to an average MOS6581

gateware-20230506

Pipelining

This is a major rewrite, pipelining all modules in the SID chip in order to
save FPGA resources:

* Power-on initialization of oscillators, noise LFSRs, and envelope counters
* Register writes
* Update and synchronization of oscillators
* Waveform generation
* Envelope generation
* Voice DCA
* Filter / audio output

gateware-20230404

Hotfix for safe POT discharge

* Mapping of SID 2 to any or all of D420, D500, and DE00 (make SID2=1)
* Linting of the complete design with Verilator and Slang
* Configurable LFSR envelope counter logic
* Corrections to MOS8580 triangle waveform timing
* Safe POT discharge - thanks to @sorgelig for raising the issue

gateware-20221211

First gateware release