ARM-Based Pipelined CPU

Overview

This project implements a 64-bit ARM-compatible pipelined processor using a 5-stage datapath architecture:

• IF (Instruction Fetch)
• ID (Instruction Decode)
• EX (Execute)
• MEM (Memory Access)
• WB (Write Back)

The CPU is built using synthesizable SystemVerilog RTL components, supporting dynamic forwarding, hazard detection, stalling, and real-time writeback for cycle-accurate execution.

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Features

• Fully synthesizable RTL design (SystemVerilog)
• Five-stage pipelined datapath (IF → ID → EX → MEM → WB)
• Dynamic data forwarding to resolve data hazards
• Load-use hazard detection and stalling
• Modular design with reusable components
• Instruction and data memory modules
• Sign extension and control signal generation
• Compatible with testbench simulation

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Pipeline Stages

1. Instruction Fetch (IF)

• Fetches instructions from instruction memory
• Maintains and updates the program counter

2. Instruction Decode (ID)

• Decodes instructions
• Reads source registers from the register file
• Performs sign extension for immediate values
• Generates control signals

3. Execute (EX)

• Performs ALU operations (e.g., ADD, SUB, AND, OR)
• Includes forwarding unit to resolve RAW hazards

4. Memory Access (MEM)

• Accesses data memory for loads and stores

5. Write Back (WB)

• Writes results back to the register file

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Files and Modules

File	Description
alu.sv	64-bit ALU supporting arithmetic/logic ops
control.sv	Control signal generator based on opcode
regfile.sv	32×64-bit register file with two read ports
forwarding_unit.sv	Data hazard resolution via forwarding logic
sign_extension.sv	Immediate value sign-extension module
instruc_fetch.sv	Instruction fetch logic with PC update
instructmem.sv	Instruction memory (read-only)
datamem.sv	Data memory for load/store instructions
D_FF.sv	D flip-flop module for pipeline registers
single_cycle_cpu.sv	Reference single-cycle CPU (for comparison)

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Simulated through ModelSim