v0.2.0 - User Space & Hardware Privilege Isolation.
Daxo OS v0.2.0 - Milestone: Ring 3 Transition & Memory Protection
We have successfully implemented the foundation for User Space isolation and CPU privilege ring switching!
馃殌 Key Features & Architectural Changes:
- Hardware Privilege Rings (Ring 0 -> Ring 3): Configured GDT (Global Descriptor Table) and TSS (Task State Segment) to support user-mode execution.
- Safe Context Switching: Implemented standard iretq assembly stack framing inside jump_to_user_space to securely drop CPU privileges.
- Memory Paging Security: Configured custom memory mapping using PageTableFlags::USER_ACCESSIBLE to safely isolate kernel-space memory from user-space execution blocks.
- Architecture Integrity: Fully resolved E0609 compile-time errors and exposed the Selectors structure for future process manager integration.
馃洜 Tech Stack Involved:
- Rust Nightly (no_std environment)
- x86_64 architecture registers manipulation
- Inline assembly (core::arch::asm!)