[Deepin-Kernel-SIG] [linux 6.6-y] [HISI] [Backport] Backport FEAT_NMI/perf DDRC/perf CORE/perf uncore/perf BRBE/minios/FEAT_HAFT and FEAT_LS64 module for Kunpeng new SOC

[Avenger-285714]

Summary by Sourcery

Add arm64 architectural NMI (FEAT_NMI / GICv3 NMI) support and integrate it with the GICv3 IRQ chip, core exception/IRQ handling, and KVM while keeping pseudo-NMI as a fallback where hardware NMI is unavailable.

New Features:

• Enable detection and use of architectural NMIs via ID_AA64PFR1.NMI for arm64 CPUs.
• Wire GICv3 FEAT_GICv3_NMI support into the irqchip to deliver NMIs using the new NMI interrupt registers and handler hooks.
• Introduce core arm64 NMI entry/exit handling paths for EL0/EL1 IRQ/FIQ, including root NMI handler registration APIs.
• Expose a system_uses_nmi() capability flag to allow core code and drivers to adapt behaviour when hardware NMIs are available.

Enhancements:

• Refine pseudo-NMI support in the GICv3 driver so it coexists cleanly with hardware NMIs and is only enabled when architectural NMI is not used.
• Extend DAIF and local IRQ flag handling, including ALLINT programming, so that masking of normal interrupts does not unintentionally mask NMIs.
• Adjust EL2/KVM trap configuration so that ALLINT is not trapped when NMIs are supported and is restored appropriately when exiting guests.
• Sanitise ID_AA64PFR1.NMI exposure to guests and add NMI to the ID register override and cpu capabilities tooling.

[sourcery-ai]

Reviewer's Guide

Backports ARM64 FEAT_NMI / GICv3 NMI support and integrates it with the existing GICv3 pseudo-NMI implementation, wiring architected NMIs through the irqchip, entry, cpufeature, and KVM paths so Kunpeng SoCs with GICD_TYPER.NMI can use hardware NMIs while preserving existing pseudo-NMI behaviour elsewhere.

Sequence diagram for ARM64 FEAT_NMI IRQ handling via GICv3

sequenceDiagram
    participant CPU as CPU_core
    participant GIC as GICv3_irqchip
    participant Entry as entry_common_el1
    participant Root as irq_root_handlers
    participant GICNMI as gic_handle_nmi_irq
    participant CoreNMI as __gic_handle_nmi
    participant Gen as generic_handle_domain_nmi

    CPU->>GIC: Hardware_superpriority_IRQ(FEAT_NMI)
    GIC-->>CPU: Signal_exception_to_EL1

    CPU->>Entry: el1h_64_irq_handler
    Entry->>Entry: el1_interrupt(regs, ISR_EL1_IS, handle_arch_irq, handle_arch_nmi_irq)
    Entry->>Entry: read_sysreg(isr_el1) & ISR_EL1_IS
    alt NMI_pending
        Entry->>CoreNMI: __el1_nmi(regs, handle_arch_nmi_irq)
        CoreNMI->>Root: handle_arch_nmi_irq(regs)
        Root->>GICNMI: gic_handle_nmi_irq(regs)
        GICNMI->>GICNMI: irqnr = gic_read_nmiar()
        GICNMI->>CoreNMI: __gic_handle_nmi(irqnr, regs)
        CoreNMI->>Gen: generic_handle_domain_nmi(gic_data.domain, irqnr)
        alt NMI_handled
            Gen-->>CoreNMI: handled
            CoreNMI-->>CPU: return_from_exception
        else Unexpected_NMI
            Gen-->>CoreNMI: not_handled
            CoreNMI->>GIC: gic_deactivate_unhandled(irqnr)
            CoreNMI-->>CPU: return_from_exception
        end
    else No_NMI_pending
        Entry->>Root: handle_arch_irq(regs)
        Root-->>CPU: handle_regular_IRQ
    end

Loading

Sequence diagram for GICv3 NMI configuration and selection vs pseudo-NMI

sequenceDiagram
    participant CPU as Boot_CPU
    participant CPFeat as cpufeature_init
    participant GIC as gic_v3_init
    participant IRQCore as irq_core

    CPU->>CPFeat: arm64_features_probe()
    CPFeat->>CPFeat: detect ARM64_HAS_NMI from ID_AA64PFR1_EL1.NMI
    CPFeat->>CPFeat: use_nmi() decides ARM64_USES_NMI
    CPFeat->>CPFeat: nmi_enable() when ARM64_USES_NMI
    CPFeat->>CPFeat: system_uses_nmi() enabled

    CPU->>GIC: gic_init_bases()
    GIC->>GIC: read GICD_TYPER
    GIC->>GIC: gic_data.has_nmi = !!(typer & GICD_TYPER_NMI)
    GIC->>GIC: gic_enable_nmi_support()
    alt HW_FEAT_NMI_available
        GIC->>GIC: has_v3_3_nmi() == true
        GIC->>GIC: allocate ppi_nmi_refs
        GIC->>GIC: skip gic_enable_pseudo_nmis()
    else Only_pseudo_NMI_available
        GIC->>GIC: has_v3_3_nmi() == false
        GIC->>GIC: gic_enable_pseudo_nmis()
        GIC->>GIC: static_branch_enable(supports_pseudo_nmis)
    end
    GIC->>IRQCore: gic_setup_nmi_handler()
    alt HW_FEAT_NMI_available
        GIC->>IRQCore: set_handle_nmi_irq(gic_handle_nmi_irq)
    else No_HW_NMI
        GIC-->>IRQCore: do_not_register_nmi_handler
    end

Loading

Class diagram for key structs and helpers in ARM64 NMI support

classDiagram
    class gic_chip_data {
        +u32 nr_redist_regions
        +u64 flags
        +bool has_rss
        +bool has_nmi
        +unsigned int ppi_nr
        +partition_desc** ppi_descs
    }

    class cpufeature_helpers {
        +bool system_uses_irq_prio_masking()
        +bool system_uses_nmi()
    }

    class gic_nmi_support {
        +void gic_irq_configure_nmi(struct irq_data* d, bool enable)
        +void gic_irq_enable_nmi(struct irq_data* d)
        +void gic_irq_disable_nmi(struct irq_data* d)
        +int gic_irq_nmi_setup(struct irq_data* d)
        +void gic_irq_nmi_teardown(struct irq_data* d)
        +bool gic_supports_pseudo_nmis()
        +bool has_v3_3_nmi()
        +void gic_enable_pseudo_nmis(void)
        +void gic_enable_nmi_support(void)
        +void gic_setup_nmi_handler(void)
    }

    class arch_nmi_core {
        +void default_handle_nmi_irq(struct pt_regs* regs)
        +void default_handle_nmi_fiq(struct pt_regs* regs)
        +int set_handle_nmi_irq(void (*handle_nmi_irq)(struct pt_regs*))
        +void (*handle_arch_nmi_irq)(struct pt_regs*)
        +void (*handle_arch_nmi_fiq)(struct pt_regs*)
    }

    class entry_common_nmi {
        +void __el1_nmi(struct pt_regs* regs, void (*handler)(struct pt_regs*))
        +void el1_interrupt(struct pt_regs* regs, u64 nmi_flag,
                           void (*handler)(struct pt_regs*),
                           void (*nmi_handler)(struct pt_regs*))
        +void el0_interrupt(struct pt_regs* regs, u64 nmi_flag,
                           void (*handler)(struct pt_regs*),
                           void (*nmi_handler)(struct pt_regs*))
    }

    class nmi_asm_helpers {
        +void _allint_clear()
        +void _allint_set()
    }

    gic_chip_data --> gic_nmi_support : used_by
    cpufeature_helpers --> gic_nmi_support : controls_has_v3_3_nmi
    gic_nmi_support --> arch_nmi_core : calls_set_handle_nmi_irq
    arch_nmi_core --> entry_common_nmi : called_from_entry
    nmi_asm_helpers --> entry_common_nmi : ALLINT_control
    nmi_asm_helpers --> gic_nmi_support : ALLINT_control_for_handlers
    cpufeature_helpers --> entry_common_nmi : system_uses_nmi

Loading

File-Level Changes

Change	Details	Files
Extend GICv3 irqchip to detect and use FEAT_GICv3_NMI for hardware NMIs alongside existing pseudo-NMI support.	Add has_nmi flag to gic_chip_data and detect GICD_TYPER.NMI during GIC init. Introduce has_v3_3_nmi() and use it in NMI setup/teardown paths to gate use of hardware NMI vs pseudo-NMI. Add GICD_INMIR/GICR_INMIR register support and implement gic_irq_configure_nmi()/enable/disable to program NMI routing with locking. Update NMI setup/teardown, RPR-priority checks, and NMI warning messages to distinguish pseudo-NMI from hardware NMI. Split gic_enable_nmi_support() so pseudo-NMIs are only enabled when FEAT_NMI/GICv3 NMI are not available, and register a GIC NMI handler via gic_setup_nmi_handler().	drivers/irqchip/irq-gic-v3.c include/linux/irqchip/arm-gic-v3.h
Plumb architected NMI capability, enable logic, and ALLINT control into the ARM64 core, including CPU feature detection and DAIF/irqflag handling.	Expose ID_AA64PFR1_EL1.NMI as a CPU feature field and add ARM64_HAS_NMI/ARM64_USES_NMI cpucaps with matching and cpu_enable hooks. Implement nmi_enable() to configure SCTLR_EL1.NMI/SPINTMASK and clear ALLINT, and add system_uses_nmi() helper. Introduce SYS_ALLINT_{SET,CLR} definitions and inline helpers _allint_set/_allint_clear in asm/nmi.h for ALLINT manipulation. Ensure DAIF helpers (local_daif_mask, local_daif_restore, local_daif_inherit) and assembler macros (disable_daif/enable_daif) coordinate ALLINT with PSTATE and tracing. Update the arm64 hard lockup watchdog availability check to also account for hardware NMI availability.	arch/arm64/kernel/cpufeature.c arch/arm64/include/asm/cpufeature.h arch/arm64/include/asm/daifflags.h arch/arm64/include/asm/assembler.h arch/arm64/kernel/watchdog_hld.c arch/arm64/include/asm/nmi.h arch/arm64/include/asm/sysreg.h
Route architected NMIs through the generic interrupt entry/IRQ core and provide root NMI handlers, including integration with GICv3 and preemption logic.	Extend entry-common interrupt paths (EL1/EL0, IRQ/FIQ) to detect NMI via ISR_EL1.{IS,FS}, dispatch to separate NMI handlers, and wrap execution in arm64_enter_nmi()/arm64_exit_nmi(). Guard preemption entry in arm64_preempt_schedule_irq() when in an NMI context using ALLINT and system_uses_nmi(). Introduce handle_arch_nmi_irq/handle_arch_nmi_fiq function pointers with default panic handlers and a set_handle_nmi_irq() registration API. Add GIC NMI read (ICC_NMIAR1_EL1) and handler wiring so GICv3 can deliver NMIs through the new NMI path, including clearing ALLINT on return when FEAT_NMI is in use. Ensure GIC IRQ handling and CPU sysreg init distinguish pseudo-NMI from hardware NMI, and avoid handling normal IRQs in an NMI-disabled context with hardware NMI.	arch/arm64/kernel/entry-common.c arch/arm64/kernel/irq.c drivers/irqchip/irq-gic-v3.c arch/arm64/include/asm/irq.h
Integrate FEAT_NMI with EL2/KVM and ID register handling so guests don’t see or trap host NMI facilities.	During EL2 finalisation and KVM trap activation/deactivation, configure HCRX_EL2.TALLINT so EL1 ALLINT accesses are not trapped when host NMI is present, and trap them when running guests. Mask ID_AA64PFR1_EL1.NMI from KVM’s sanitised ID register so guests do not see NMI support. Document and plumb ID_AA64PFR1_EL1.NMI into the ID override infrastructure and cpucaps tooling.	arch/arm64/kernel/hyp-stub.S arch/arm64/kvm/hyp/include/hyp/switch.h arch/arm64/kvm/sys_regs.c arch/arm64/kernel/idreg-override.c arch/arm64/tools/cpucaps Documentation/arch/arm64/booting.rst arch/arm64/Kconfig
Minor correctness and API changes related to interrupt state helpers.	Fix fast_interrupts_enabled() macro to correctly test PSR_F_BIT without extraneous parentheses. Add prototypes/exports for the NMI handler registration API in asm/irq.h. Adjust comments in irqflags to clarify that NMIs are not covered by standard IRQ masking semantics.	arch/arm64/include/asm/ptrace.h arch/arm64/include/asm/irqflags.h arch/arm64/include/asm/irq.h

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[deepin-ci-robot]

[APPROVALNOTIFIER] This PR is NOT APPROVED

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Once this PR has been reviewed and has the lgtm label, please ask for approval from avenger-285714. For more information see the Code Review Process.

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[sourcery-ai]

Hey - I've left some high level feedback:

• The change to fast_interrupts_enabled in arch/arm64/include/asm/ptrace.h drops the inner parentheses and changes the expression semantics from testing the PSR_F_BIT to (!pstate) & PSR_F_BIT, which will mis-detect FIQ state; restore the original parenthesisation so the macro still checks (regs->pstate & PSR_F_BIT).
• The new helpers in arch/arm64/include/asm/nmi.h use asm volatile(__msr_s(SYS_ALLINT_CLR, "xzr"));/__msr_s(SYS_ALLINT_SET, ...) inside the asm string, which does not match how sysreg access macros are normally used and is unlikely to assemble correctly; reuse the existing msr_s/sysreg_* macros or emit a plain msr_s instruction string with _stringify(SYS_ALLINT*).

Prompt for AI Agents

Please address the comments from this code review:

## Overall Comments
- The change to fast_interrupts_enabled in arch/arm64/include/asm/ptrace.h drops the inner parentheses and changes the expression semantics from testing the PSR_F_BIT to `(!pstate) & PSR_F_BIT`, which will mis-detect FIQ state; restore the original parenthesisation so the macro still checks `(regs->pstate & PSR_F_BIT)`.
- The new helpers in arch/arm64/include/asm/nmi.h use `asm volatile(__msr_s(SYS_ALLINT_CLR, "xzr"));`/`__msr_s(SYS_ALLINT_SET, ...)` inside the asm string, which does not match how sysreg access macros are normally used and is unlikely to assemble correctly; reuse the existing `msr_s`/`sysreg_*` macros or emit a plain `msr_s` instruction string with __stringify(SYS_ALLINT_*).

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[Avenger-285714]

Note: the commit ("locking/qspinlock: Add CNA support for ARM64 without pvspinlock") and ("Revert "deepin: qspinlock: Disable CNA by default"") modifies out‑of‑tree patches from other vendors and requires careful review.

Link: #692

[Avenger-285714]

@sourcery-ai review

[sourcery-ai]

Sorry @Avenger-285714, your pull request is larger than the review limit of 150000 diff characters

[SourceryAI]

Sorry @Avenger-285714, your pull request is larger than the review limit of 150000 diff characters

[Copilot]

Pull request overview

Copilot reviewed 109 out of 109 changed files in this pull request and generated 3 comments.

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💡 Add Copilot custom instructions for smarter, more guided reviews. Learn how to get started.

[Copilot]

ALLINT_ALLINT is used here to test the ALLINT field, but there is no definition of this macro in the tree, so this code will not compile. A proper bitmask definition for the ALLINT field (in the same style as other sysreg field masks) needs to be added, or this test should use whatever generated field macro exists once the ALLINT register is described in sysreg-defs.

[Copilot]

The new select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAF line references a Kconfig symbol ARM64_HAF that does not exist (the feature config added below is ARM64_HAFT and the existing AF/DBM option is ARM64_HW_AFDBM). This will cause Kconfig warnings or errors and prevent the intended selection from taking effect; the condition should be updated to use the correct symbol name (likely ARM64_HAFT).

Suggested change

	select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAF
	select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT

[Copilot]

SYS_ALLINT is used with read_sysreg_s() here but is never defined in sysreg.h (only SYS_ALLINT_CLR and SYS_ALLINT_SET exist), which will cause a build failure. Either a readable SYS_ALLINT alias needs to be defined with the correct encoding for the ALLINT system register, or this code should be updated to read from the appropriate existing system register instead.

Suggested change

	*/
	if (system_uses_nmi() && (read_sysreg_s(SYS_ALLINT) & ALLINT_ALLINT))
	return;
	*/
	#ifdef SYS_ALLINT
	if (system_uses_nmi() && (read_sysreg_s(SYS_ALLINT) & ALLINT_ALLINT))
	return;
	#endif