Quiver v0.7.0

Quiver v0.7.0 — Apple M2 performance closure, sub-byte unpack, release-path repair

The single-machine performance story is closed: every Apple M2 operation shape dispatches to the
fastest correct implementation with committed evidence, and this is the first tag whose release
pipeline ran green end to end — full CI gate, three-platform differential sweep, 4.5 h
differential fuzz, MSan (fixed this release, R-19), LSan — and published its artifacts.

What changed?

• Vectorized sub-byte bit-unpack (widths 1–7) promoted to production dispatch: 6.9×–11.0×
  over the scalar gather on Apple M2, exact ⌈n·w/8⌉ read bound preserved and guard-page proven.
• Evidence-gated delegations on aarch64: 64-bit compare bitmap and 8-byte elementwise
  arithmetic run the compiler's code where it measured faster (parity verified at every registered
  shape); narrow-width compare (i8/i16/i32) measured and stays handwritten (2.8×/1.6×/1.1× wins).
• Complete Apple M2 paired benchmark grid: 53 shapes, zero unknowns; dense-i64-sum parity and
  null-masked wins up to 8.39× recorded honestly.
• Nightly MSan leg fixed (R-19 closed): the release publish path is live for the first time.
• Full details: CHANGELOG ·
  release notes.

Did the API change?

No. All public signatures unchanged (the M10 freeze audit remains clean). Dispatch behavior
changes only in which backend runs for the affected shapes; results are bit-identical everywhere.

Which platforms passed?

Linux x86-64 (GCC 13/14, Clang 17/19), Linux ARM64 (GCC 14, Clang 19), macOS ARM64 (Apple Clang)
— full suite. AVX-512 correctness under Intel SDE (-spr, -skx). MSVC amalgamation (tier-2,
default /arch, two documented exclusions). The matrix with compiles/tested/measured kept
distinct: compatibility.

Which machines were measured?

One: Apple M2 (apple-m2-mba, secondary platform, no PMU). Every number above is from that
machine's committed ledger and no cross-CPU claim is made. Registering an x86 machine is the most
valuable contribution the project can receive:
#38 / #39.

What remains unverified?

Native AVX-512 performance (no hardware), x86 performance generally, Windows performance; v1.0
certification is deferred until the multi-machine coverage and regression gates can run (R-06).
The status report keeps
the full honest list.

How do I install it?

• Two files, one command (attached below): download quiver.h + quiver.cpp, then
  c++ -std=c++23 -O3 your_app.cpp quiver.cpp — the
  30-second quickstart
  was compile-run verified against these exact artifacts.
• CMake: FetchContent from this tag, or find_package(Quiver CONFIG) after install.
• vcpkg / Conan Center submissions are staged
  (#40, #41).

Verifying the artifacts

SHA256SUMS covers every attached file; each artifact carries a GitHub build-provenance
attestation: gh attestation verify <file> --repo div0rce/quiver. Both were verified before this
release was published.

v0.3.0 — Tier A NEON + Performance Ledger (public launch)

Quiver's public-launch release (the charter's 9-month shrink point — the repository state is certified releasable-as-final).

NEON backends for all six Tier A kernel families — runtime-dispatched on ARM64, bit-identical to the scalar references (dense float sums follow the documented ADR-013 blocked policy), validated by the differential matrix and ~1M+ differential-fuzz executions per family under ASan+UBSan.

The performance ledger ships as a product: QLS-1 schemas, a reproducible stdlib-only runner (seeded percentile-bootstrap statistics, fresh-process shuffled repetitions, environment manifests, append-only results), and the first committed results from the registered Apple M2 (secondary platform, honestly flagged).

Verdicts — wins AND losses (neon vs autovec, Apple M2, geomean over published pairs): filter 1.72×, select 7.59×, reduce 4.43× (f64 blocked sums ~8× vs the strict baseline — see the ADR-013 caveat), mask 0.97× parity, take 1.00× parity (no gather on NEON, by design), compare 0.69× — the autovec baseline wins, published as measured per the Charter T7 pledge.

Coverage honesty: one registered microarchitecture at launch; the three-µarch gate (Zen 4/5, Golden Cove) is an open, recorded deferral — no numbers are invented. Reproduction: dispute guide.

Full notes: docs/releases/v0.3.0.md · Gate record: docs/releases/gates/M5.md

v0.2.0 — Tier A AVX2

First explicit-SIMD tier: AVX2 backends for all six Tier A kernel families (runtime-dispatched on AVX2+BMI2 x86-64, bit-identical to the scalar references), differential libFuzzer targets for every family with committed corpora and enforced CI fuzz-smoke, equal-ISA autovec-avx2 benchmark baselines (ADR-011), and the ADR-013 blocked float-sum policy with its testkit oracle.

Fixed: empty selection vectors (SelVec{nullptr, 0}) were misread as "no selection" by the K5/K6 concrete symbols — memory-unsafe in fused dict_decode; found by the first differential-fuzzing session, fixed and regression-locked.

Full notes: docs/releases/v0.2.0.md · Gate record: docs/releases/gates/M4.md

No performance numbers are published in this release (Charter T2): the first ledger publication is v0.3.

v0.1.0 — Tier A scalar kernels

Release v0.1.0

Date: 2026-07-03 · Milestones completed: M0 (bootstrap), M1 (core + CPU detection + dispatch), M2 (testkit + bench harness), M3 (Tier A scalar kernels). Release template per REQ-DOC-010.

Summary

The first tagged release: all six Tier A kernel families — K1 compare, K2 filter, K3 sel_convert, K4 mask_algebra, K5 take/dict_decode, K6 reduce/SMA — implemented as readable scalar reference specifications behind the runtime-dispatch framework, with the complete contract surface (Surface B vocabulary types, Surface C dispatch/introspection), dual-oracle test stack (71 tests: unit, property, differential-vs-naive, invariant, guard-page, no-allocation), validated benchmarks, and CI across x86-64/ARM64/macOS with ASan/UBSan/TSan.

Completed requirements

All requirement IDs allocated to M0–M3 per PRD 01 §6 / 18; per-milestone lists in the gate records (M0, M1, M2, M3).

API changes

Initial public surface (0.x-fluid until v1.0): quiver/core.h, quiver/dispatch.h, and the six Tier A family headers. 176 concrete dispatched symbols behind template facades (ADR-006).

Benchmark / ledger changes

Family + dispatch-overhead benchmarks exist and validate before timing (REQ-BENCH-004). No ledger yet and therefore no published performance numbers (Charter T2): the first ledger publication is v0.3 (M5).

ADR changes

None (all 26 remain Accepted; ADR-013 realized with the scalar strict-fold recourse).

Known limitations

Scalar backends only — explicit SIMD lands at M4 (AVX2), M5 (NEON), M7 (AVX-512). No install/package/amalgamation until M8 (consume via add_subdirectory/FetchContent). Tier B families (hash, unpack, arith, arith_guarded) arrive at M6. Real-PMU benchmark evidence deferred to registered ledger machines (M5). MSVC remains tier-2 best-effort.

Migration notes

None (first release).