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LSRA: Consider a stress mode that trashes registers #10691
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area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMICLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMIhelp wanted[up-for-grabs] Good issue for external contributors[up-for-grabs] Good issue for external contributorstenet-reliabilityReliability/stability related issue (stress, load problems, etc.)Reliability/stability related issue (stress, load problems, etc.)test-enhancementImprovements of test source codeImprovements of test source code
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area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMICLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMIhelp wanted[up-for-grabs] Good issue for external contributors[up-for-grabs] Good issue for external contributorstenet-reliabilityReliability/stability related issue (stress, load problems, etc.)Reliability/stability related issue (stress, load problems, etc.)test-enhancementImprovements of test source codeImprovements of test source code
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The issue https://github.com/dotnet/coreclr/issues/18943 is a case where it appears a register is being incorrectly copied to the wrong register before its intended use. If we had a
COMPlus_JitStressRegsmode that would write some trash value to each register when it goes dead, a case like this might have been caught.category:implementation
theme:register-allocator
skill-level:beginner
cost:small