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JIT: If-conversion costing rejects (cond ? 1 << a : 0) even on RISCV where this gets explicitly targeted #127110

@BoyBaykiller

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@BoyBaykiller

We have this optimization in if-conversion that turns SELECT(cond, 1 << a, 0) into cond << a. It only runs on RISCV:

// TryTransformSelectToOrdinaryOps: Try transforming the identified if-else expressions to a single expression
//
// This is meant mostly for RISC-V where the condition (1 or 0) is stored in a regular general-purpose register
// which can be fed as an argument to standard operations, e.g.
// * (cond ? 6 : 5) becomes (5 + cond)
// * (cond ? -25 : -13) becomes (-25 >> cond)
// * if (cond) a++; becomes (a + cond)
// * (cond ? 1 << a : 0) becomes (cond << a)

However our current cost-analysis always rejects such patterns. Example:

int Cond1Shift(bool cond, int a)
{
    return cond ? (1 << a) : 0;
}

If we look at JitDump:

***** BB03 [0002]
STMT00001 ( 0x005[E--] ... 0x00B )
N006 ( 11,  9) [000009] -----+-----                         *  RETURN    int    $VN.Void
N005 ( 10,  8) [000008] -----+--R--                         \--*  LSH       int    $143
N004 (  1,  2) [000004] -----+-----                            +--*  CNS_INT   int    1 $41
N003 (  5,  5) [000007] -----+-----                            \--*  AND       int    $142
N001 (  3,  2) [000005] -----+-----                               +--*  LCL_VAR   int    V01 arg1         u:1 (last use) $c0
N002 (  1,  2) [000006] -----+-----                               \--*  CNS_INT   int    31 $44
Skipping if-conversion that will evaluate RHS unconditionally at costs 1,10

So the optimization above for RISCV is essentially dead code. We always bail out earlier which is probably not wanted.

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area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMIuntriagedNew issue has not been triaged by the area owner

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