[JIT] Bool optimization case

[TIHan]

    public static void TestBoolAsg(int a, int b, int c, ref bool z)
    {
        z = a == 0 && b == 0 && c == 0;
    }

When comparing the JIT output to this:

    public static bool TestBoolReturn(int a, int b, int c)
    {
        return a == 0 && b == 0 && c == 0;
    }

TestBoolAsg is as not as optimized as TestBoolReturn:

// TestBoolAsg
G_M56616_IG02:              ;; offset=0000H
       0BD1                 or       edx, ecx
       750A                 jne      SHORT G_M56616_IG04
						;; size=4 bbWeight=1 PerfScore 1.25

G_M56616_IG03:              ;; offset=0004H
       33C0                 xor      eax, eax
       4585C0               test     r8d, r8d
       0F94C0               sete     al
       EB02                 jmp      SHORT G_M56616_IG05
						;; size=10 bbWeight=0.50 PerfScore 1.75

G_M56616_IG04:              ;; offset=000EH
       33C0                 xor      eax, eax
						;; size=2 bbWeight=0.50 PerfScore 0.12

G_M56616_IG05:              ;; offset=0010H
       418801               mov      byte  ptr [r9], al
						;; size=3 bbWeight=1 PerfScore 1.00

G_M56616_IG06:              ;; offset=0013H
       C3                   ret   

vs.

// TestBoolReturn
G_M58330_IG02:              ;; offset=0000H
       0BD1                 or       edx, ecx
       410BD0               or       edx, r8d
       0F94C0               sete     al
       0FB6C0               movzx    rax, al
						;; size=11 bbWeight=1 PerfScore 1.75

G_M58330_IG03:              ;; offset=000BH
       C3                   ret 

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Issue Details

---

    public static void TestBoolAsg(int a, int b, int c, ref bool z)
    {
        z = a == 0 && b == 0 && c == 0;
    }

When comparing the JIT output to this:

    public static bool TestBoolReturn(int a, int b, int c)
    {
        return a == 0 && b == 0 && c == 0;
    }

TestBoolAsg is as not as optimized as TestBoolReturn:

// TestBoolAsg
G_M56616_IG02:              ;; offset=0000H
       0BD1                 or       edx, ecx
       750A                 jne      SHORT G_M56616_IG04
						;; size=4 bbWeight=1 PerfScore 1.25

G_M56616_IG03:              ;; offset=0004H
       33C0                 xor      eax, eax
       4585C0               test     r8d, r8d
       0F94C0               sete     al
       EB02                 jmp      SHORT G_M56616_IG05
						;; size=10 bbWeight=0.50 PerfScore 1.75

G_M56616_IG04:              ;; offset=000EH
       33C0                 xor      eax, eax
						;; size=2 bbWeight=0.50 PerfScore 0.12

G_M56616_IG05:              ;; offset=0010H
       418801               mov      byte  ptr [r9], al
						;; size=3 bbWeight=1 PerfScore 1.00

G_M56616_IG06:              ;; offset=0013H
       C3                   ret   

vs.

// TestBoolReturn
G_M58330_IG02:              ;; offset=0000H
       0BD1                 or       edx, ecx
       410BD0               or       edx, r8d
       0F94C0               sete     al
       0FB6C0               movzx    rax, al
						;; size=11 bbWeight=1 PerfScore 1.75

G_M58330_IG03:              ;; offset=000BH
       C3                   ret 

Author:	TIHan
Assignees:	-
Labels:	help wanted, area-CodeGen-coreclr
Milestone:	Future

[hopperpl]

this pattern would be even better:

    xor   eax, eax
    sete  al

The xor instruction is a nop (0 cycles) as the instruction decoder recognizes this to be a zeroing register instruction. But this has to be reordered because xor modifies flags (swap with the prior or in this case is good enough). Using xor also removes the delay between sete and movzx.