JIT: Handle writes to promoted locals in AliasSet::AddNode

[jakobbotsch]

Fix #126414

Codegen diff (with some PRs reverted to repro the original problem on main):

@@ -1,71 +1,72 @@
 ; Assembly listing for method Range:.ctor(Endpoint,Endpoint):this (FullOpts)
 ; Emitting BLENDED_CODE for arm64 + SVE on Windows
 ; FullOpts code
 ; optimized code
 ; optimized using Synthesized PGO
 ; fp based frame
 ; partially interruptible
 ; with Synthesized PGO: fgCalledCount is 100
 ; No matching PGO data
 ; 0 inlinees with PGO data; 9 single block inlinees; 0 inlinees without PGO data
 ; Final local variable assignments
 ;
 ;  V00 this         [V00,T00] (  8,  8   )     ref  ->   x0         this class-hnd single-def <Range>
 ;* V01 arg1         [V01    ] (  0,  0   )  struct (16) zero-ref    do-not-enreg[SA] multireg-arg single-def <Endpoint>
 ;* V02 arg2         [V02    ] (  0,  0   )  struct (16) zero-ref    do-not-enreg[SA] multireg-arg single-def <Endpoint>
 ;# V03 OutArgs      [V03    ] (  1,  1   )  struct ( 0) [sp+0x00]   do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
 ;* V04 tmp1         [V04    ] (  0,  0   )  struct (16) zero-ref    ld-addr-op "NewObj constructor temp" <Endpoint>
 ;* V05 tmp2         [V05    ] (  0,  0   )  struct (16) zero-ref    ld-addr-op "NewObj constructor temp" <Endpoint>
 ;  V06 tmp3         [V06    ] (  5, 10   )  struct (16) [fp+0x20]   do-not-enreg[SF] ld-addr-op "Inlining Arg" <Endpoint>
 ;  V07 tmp4         [V07    ] (  5, 10   )  struct (16) [fp+0x10]   do-not-enreg[SF] ld-addr-op "Inlining Arg" <Endpoint>
 ;* V08 tmp5         [V08    ] (  0,  0   )     int  ->  zero-ref    "field V04.<A>k__BackingField (fldOffset=0x0)" P-INDEP
 ;* V09 tmp6         [V09    ] (  0,  0   )     int  ->  zero-ref    "field V04.<B>k__BackingField (fldOffset=0x4)" P-INDEP
 ;* V10 tmp7         [V10    ] (  0,  0   )     int  ->  zero-ref    "field V04.<C>k__BackingField (fldOffset=0x8)" P-INDEP
 ;* V11 tmp8         [V11    ] (  0,  0   )     int  ->  zero-ref    "field V05.<A>k__BackingField (fldOffset=0x0)" P-INDEP
 ;* V12 tmp9         [V12    ] (  0,  0   )     int  ->  zero-ref    "field V05.<B>k__BackingField (fldOffset=0x4)" P-INDEP
 ;* V13 tmp10        [V13    ] (  0,  0   )     int  ->  zero-ref    "field V05.<C>k__BackingField (fldOffset=0x8)" P-INDEP
 ;  V14 tmp11        [V14,T07] (  2,  3   )     int  ->  [fp+0x20]   do-not-enreg[] "field V06.<A>k__BackingField (fldOffset=0x0)" P-DEP
 ;  V15 tmp12        [V15,T08] (  2,  3   )     int  ->  [fp+0x24]   do-not-enreg[] "field V06.<B>k__BackingField (fldOffset=0x4)" P-DEP
 ;  V16 tmp13        [V16,T01] (  3,  4   )     int  ->  [fp+0x28]   do-not-enreg[] "field V06.<C>k__BackingField (fldOffset=0x8)" P-DEP
 ;  V17 tmp14        [V17,T09] (  2,  3   )     int  ->  [fp+0x10]   do-not-enreg[] "field V07.<A>k__BackingField (fldOffset=0x0)" P-DEP
 ;  V18 tmp15        [V18,T10] (  2,  3   )     int  ->  [fp+0x14]   do-not-enreg[] "field V07.<B>k__BackingField (fldOffset=0x4)" P-DEP
 ;  V19 tmp16        [V19,T02] (  3,  4   )     int  ->  [fp+0x18]   do-not-enreg[] "field V07.<C>k__BackingField (fldOffset=0x8)" P-DEP
 ;  V20 tmp17        [V20,T11] (  2,  2   )     int  ->   x2         "V01.[008..012)"
 ;  V21 tmp18        [V21,T12] (  2,  2   )     int  ->   x4         "V02.[008..012)"
 ;  V22 rat0         [V22,T03] (  3,  3   )    long  ->   x2         "V01.x2"
 ;  V23 rat1         [V23,T04] (  3,  3   )    long  ->   x4         "V02.x4"
 ;  V24 rat2         [V24,T05] (  3,  3   )    long  ->   x1         "V01.x1"
 ;  V25 rat3         [V25,T06] (  3,  3   )    long  ->   x3         "V02.x3"
 ;
 ; Lcl frame size = 32
 
 G_M49258_IG01:
             stp     fp, lr, [sp, #-0x30]!
             mov     fp, sp
 						;; size=8 bbWeight=1 PerfScore 1.50
 G_M49258_IG02:
             str     w2, [fp, #0x28]	// [V16 tmp13]
             str     x1, [fp, #0x20]	// [V06 tmp3]
             ldp     w1, w2, [fp, #0x20]	// [V14 tmp11], [V15 tmp12]
             stp     w1, w2, [x0, #0x08]
             ldr     w1, [fp, #0x28]	// [V16 tmp13]
-            ldr     w2, [fp, #0x10]	// [V17 tmp14]     // this read stack garbage before
-            stp     w1, w2, [x0, #0x10]
+            str     w1, [x0, #0x10]
             str     w4, [fp, #0x18]	// [V19 tmp16]
             str     x3, [fp, #0x10]	// [V07 tmp4]
-            ldp     w1, w2, [fp, #0x14]	// [V18 tmp15], [V19 tmp16]
-            stp     w1, w2, [x0, #0x18]
-						;; size=44 bbWeight=1 PerfScore 15.00
+            ldp     w1, w2, [fp, #0x10]	// [V17 tmp14], [V18 tmp15]
+            stp     w1, w2, [x0, #0x14]
+            ldr     w1, [fp, #0x18]	// [V19 tmp16]
+            str     w1, [x0, #0x1C]
+						;; size=48 bbWeight=1 PerfScore 16.00
 G_M49258_IG03:
             ldp     fp, lr, [sp], #0x30
             ret     lr
 						;; size=8 bbWeight=1 PerfScore 2.00
 
-; Total bytes of code 60, prolog size 8, PerfScore 18.50, instruction count 15, allocated bytes for code 60 (MethodHash=bb583f95) for method Range:.ctor(Endpoint,Endpoint):this (FullOpts)
+; Total bytes of code 64, prolog size 8, PerfScore 19.50, instruction count 16, allocated bytes for code 64 (MethodHash=bb583f95) for method Range:.ctor(Endpoint,Endpoint):this (FullOpts)
 ; ============================================================

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Pull request overview

This PR updates CoreCLR JIT alias tracking so that writes involving promoted locals (and their promoted field locals) are treated as interfering with related locals, preventing incorrect transformations that can lead to wrong codegen on arm64 (as in #126414).

Changes:

• Extend AliasSet::AddNode to treat writes to promoted struct-field locals as writes to the parent promoted local.
• Extend AliasSet::AddNode to treat writes to a promoted parent local as writes to all of its promoted field locals.