Replace PERFSCORE_MEMORY_* macros with PerfScoreMemoryAccessKind enum class by Copilot · Pull Request #127148 · dotnet/runtime

Copilot · 2026-04-20T11:58:12Z

Note

This pull request description was generated with AI/Copilot assistance.

Summary

Replaced PERFSCORE_MEMORY_* macro constants with PerfScoreMemoryAccessKind enum class.
Added enum members: None, Read, Write, ReadWrite.
Updated JIT perf-score code paths to use the enum type across:
- emit.h
- emit.cpp
- emitarm64.cpp
- emitxarch.cpp
- emitriscv64.cpp
- emitloongarch64.cpp
Addressed review feedback with formatting-only alignment fixes in:
- emit.h (insExecutionCharacteristics field alignment)
- emitloongarch64.cpp (INS_OPTS_RELOC assignment alignment)

Validation

Baseline build before edits: ./build.sh clr+libs+host
Post-change build: ./build.sh clr -rc checked
Parallel validation:
- Code Review: no comments
- CodeQL: no alerts reported (analysis skipped for cpp due DB size limits)
Additional formatting validation:
- Attempted jitformat.py check; blocked in this environment due clang-format tool download failure.

Notes

No direct tests were found for this debug/LATE_DISASM perf-score path; validation focused on successful CoreCLR compilation and static review/security checks.
Latest follow-up commit is formatting-only and does not change behavior.

Agent-Logs-Url: https://github.com/dotnet/runtime/sessions/db453486-2627-4fce-8b98-e726643e4dac Co-authored-by: jakobbotsch <7887810+jakobbotsch@users.noreply.github.com>

dotnet-policy-service · 2026-04-20T12:12:35Z

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
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jakobbotsch · 2026-04-20T13:39:44Z

@copilot Fix the formatting based on this patch:

diff --git a/src/coreclr/jit/emit.h b/src/coreclr/jit/emit.h
index 606a6c16..61c335a3 100644
--- a/src/coreclr/jit/emit.h
+++ b/src/coreclr/jit/emit.h
@@ -2205,42 +2205,42 @@ protected:
 #define PERFSCORE_LATENCY_WR_STACK         PERFSCORE_LATENCY_1C
 #define PERFSCORE_LATENCY_RD_WR_STACK      PERFSCORE_LATENCY_3C
 
 // a read, write or modify from constant location, possible def to use latency from L0 cache
 #define PERFSCORE_LATENCY_RD_CONST_ADDR    PERFSCORE_LATENCY_3C
 #define PERFSCORE_LATENCY_WR_CONST_ADDR    PERFSCORE_LATENCY_1C
 #define PERFSCORE_LATENCY_RD_WR_CONST_ADDR PERFSCORE_LATENCY_3C
 
 // a read, write or modify from memory location, possible def to use latency from L0 or L1 cache
 // plus an extra cost  (of 1.0) for a increased chance  of a cache miss
 #define PERFSCORE_LATENCY_RD_GENERAL       PERFSCORE_LATENCY_4C
 #define PERFSCORE_LATENCY_WR_GENERAL       PERFSCORE_LATENCY_1C
 #define PERFSCORE_LATENCY_RD_WR_GENERAL    PERFSCORE_LATENCY_4C
 
 #else
 #error Unknown TARGET
 #endif
 
     struct insExecutionCharacteristics
     {
-        float    insThroughput;
-        float    insLatency;
+        float                     insThroughput;
+        float                     insLatency;
         PerfScoreMemoryAccessKind insMemoryAccessKind;
     };
 
     float insEvaluateExecutionCost(instrDesc* id);
 
     insExecutionCharacteristics getInsExecutionCharacteristics(instrDesc* id);
 
     void perfScoreUnhandledInstruction(instrDesc* id, insExecutionCharacteristics* result);
 
 #endif // defined(DEBUG) || defined(LATE_DISASM)
 
     weight_t getCurrentBlockWeight();
 
     void dispIns(instrDesc* id);
 
     void appendToCurIG(instrDesc* id);
 
     /********************************************************************************************/
 
     struct instrDescJmp : instrDesc
diff --git a/src/coreclr/jit/emitloongarch64.cpp b/src/coreclr/jit/emitloongarch64.cpp
index 411d1505..311f84fd 100644
--- a/src/coreclr/jit/emitloongarch64.cpp
+++ b/src/coreclr/jit/emitloongarch64.cpp
@@ -5255,42 +5255,42 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
         { // xor + bnez/beqz or bnez/beqz + pcaddi + jirl
             assert((CombinedInsCnt == 2) || (CombinedInsCnt == 3));
             result.insLatency    = (CombinedInsCnt == 2) ? PERFSCORE_LATENCY_2C : PERFSCORE_LATENCY_3C;
             result.insThroughput = (CombinedInsCnt == 2) ? 5.5f : PERFSCORE_THROUGHPUT_5C;
         }
         else if (id->idInsOpt() == INS_OPTS_I)
         { // addi.d, srli.d, lu12i.w, ori, lu32i.d, lu52i.d
             result.insLatency    = PERFSCORE_LATENCY_1C * CombinedInsCnt;
             result.insThroughput = (CombinedInsCnt < 3)
                                        ? PERFSCORE_THROUGHPUT_4C * CombinedInsCnt
                                        : PERFSCORE_THROUGHPUT_4C * (CombinedInsCnt - 1) + PERFSCORE_THROUGHPUT_1C;
         }
         else if (id->idInsOpt() == INS_OPTS_C)
         { // pcaddu18i + jirl or lu12i.w + ori + lu32i.d + jirl
             assert((CombinedInsCnt == 2) || (CombinedInsCnt == 4));
             result.insLatency    = (CombinedInsCnt == 2) ? PERFSCORE_LATENCY_2C : PERFSCORE_LATENCY_4C;
             result.insThroughput = (CombinedInsCnt == 2) ? 3.5f : 10.5f;
         }
         else if (id->idInsOpt() == INS_OPTS_RELOC)
         { // pcalau12i + (addi.d or ld.d)
-            result.insLatency          = id->idIsCnsReloc() ? PERFSCORE_LATENCY_2C : PERFSCORE_LATENCY_5C;
-            result.insThroughput       = id->idIsCnsReloc() ? PERFSCORE_THROUGHPUT_6C : PERFSCORE_THROUGHPUT_4C;
+            result.insLatency    = id->idIsCnsReloc() ? PERFSCORE_LATENCY_2C : PERFSCORE_LATENCY_5C;
+            result.insThroughput = id->idIsCnsReloc() ? PERFSCORE_THROUGHPUT_6C : PERFSCORE_THROUGHPUT_4C;
             result.insMemoryAccessKind =
                 id->idIsCnsReloc() ? PerfScoreMemoryAccessKind::None : PerfScoreMemoryAccessKind::Read;
         }
         else
         {
             perfScoreUnhandledInstruction(id, &result);
         }
 
         return result;
     }
 
     assert(ins != INS_lea);
 
     if (emitInsIsLoadOrStore(ins))
     {
         if (emitInsIsLoad(ins))
         {
             result.insMemoryAccessKind =
                 emitInsIsStore(ins) ? PerfScoreMemoryAccessKind::ReadWrite : PerfScoreMemoryAccessKind::Read;
         }

jakobbotsch · 2026-04-20T13:50:53Z

@copilot Fix the formatting based on this patch:

diff --git a/src/coreclr/jit/emit.h b/src/coreclr/jit/emit.h
index 606a6c16..61c335a3 100644
--- a/src/coreclr/jit/emit.h
+++ b/src/coreclr/jit/emit.h
@@ -2205,42 +2205,42 @@ protected:
 #define PERFSCORE_LATENCY_WR_STACK         PERFSCORE_LATENCY_1C
 #define PERFSCORE_LATENCY_RD_WR_STACK      PERFSCORE_LATENCY_3C
 
 // a read, write or modify from constant location, possible def to use latency from L0 cache
 #define PERFSCORE_LATENCY_RD_CONST_ADDR    PERFSCORE_LATENCY_3C
 #define PERFSCORE_LATENCY_WR_CONST_ADDR    PERFSCORE_LATENCY_1C
 #define PERFSCORE_LATENCY_RD_WR_CONST_ADDR PERFSCORE_LATENCY_3C
 
 // a read, write or modify from memory location, possible def to use latency from L0 or L1 cache
 // plus an extra cost  (of 1.0) for a increased chance  of a cache miss
 #define PERFSCORE_LATENCY_RD_GENERAL       PERFSCORE_LATENCY_4C
 #define PERFSCORE_LATENCY_WR_GENERAL       PERFSCORE_LATENCY_1C
 #define PERFSCORE_LATENCY_RD_WR_GENERAL    PERFSCORE_LATENCY_4C
 
 #else
 #error Unknown TARGET
 #endif
 
     struct insExecutionCharacteristics
     {
-        float    insThroughput;
-        float    insLatency;
+        float                     insThroughput;
+        float                     insLatency;
         PerfScoreMemoryAccessKind insMemoryAccessKind;
     };
 
     float insEvaluateExecutionCost(instrDesc* id);
 
     insExecutionCharacteristics getInsExecutionCharacteristics(instrDesc* id);
 
     void perfScoreUnhandledInstruction(instrDesc* id, insExecutionCharacteristics* result);
 
 #endif // defined(DEBUG) || defined(LATE_DISASM)
 
     weight_t getCurrentBlockWeight();
 
     void dispIns(instrDesc* id);
 
     void appendToCurIG(instrDesc* id);
 
     /********************************************************************************************/
 
     struct instrDescJmp : instrDesc
diff --git a/src/coreclr/jit/emitloongarch64.cpp b/src/coreclr/jit/emitloongarch64.cpp
index 411d1505..311f84fd 100644
--- a/src/coreclr/jit/emitloongarch64.cpp
+++ b/src/coreclr/jit/emitloongarch64.cpp
@@ -5255,42 +5255,42 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
         { // xor + bnez/beqz or bnez/beqz + pcaddi + jirl
             assert((CombinedInsCnt == 2) || (CombinedInsCnt == 3));
             result.insLatency    = (CombinedInsCnt == 2) ? PERFSCORE_LATENCY_2C : PERFSCORE_LATENCY_3C;
             result.insThroughput = (CombinedInsCnt == 2) ? 5.5f : PERFSCORE_THROUGHPUT_5C;
         }
         else if (id->idInsOpt() == INS_OPTS_I)
         { // addi.d, srli.d, lu12i.w, ori, lu32i.d, lu52i.d
             result.insLatency    = PERFSCORE_LATENCY_1C * CombinedInsCnt;
             result.insThroughput = (CombinedInsCnt < 3)
                                        ? PERFSCORE_THROUGHPUT_4C * CombinedInsCnt
                                        : PERFSCORE_THROUGHPUT_4C * (CombinedInsCnt - 1) + PERFSCORE_THROUGHPUT_1C;
         }
         else if (id->idInsOpt() == INS_OPTS_C)
         { // pcaddu18i + jirl or lu12i.w + ori + lu32i.d + jirl
             assert((CombinedInsCnt == 2) || (CombinedInsCnt == 4));
             result.insLatency    = (CombinedInsCnt == 2) ? PERFSCORE_LATENCY_2C : PERFSCORE_LATENCY_4C;
             result.insThroughput = (CombinedInsCnt == 2) ? 3.5f : 10.5f;
         }
         else if (id->idInsOpt() == INS_OPTS_RELOC)
         { // pcalau12i + (addi.d or ld.d)
-            result.insLatency          = id->idIsCnsReloc() ? PERFSCORE_LATENCY_2C : PERFSCORE_LATENCY_5C;
-            result.insThroughput       = id->idIsCnsReloc() ? PERFSCORE_THROUGHPUT_6C : PERFSCORE_THROUGHPUT_4C;
+            result.insLatency    = id->idIsCnsReloc() ? PERFSCORE_LATENCY_2C : PERFSCORE_LATENCY_5C;
+            result.insThroughput = id->idIsCnsReloc() ? PERFSCORE_THROUGHPUT_6C : PERFSCORE_THROUGHPUT_4C;
             result.insMemoryAccessKind =
                 id->idIsCnsReloc() ? PerfScoreMemoryAccessKind::None : PerfScoreMemoryAccessKind::Read;
         }
         else
         {
             perfScoreUnhandledInstruction(id, &result);
         }
 
         return result;
     }
 
     assert(ins != INS_lea);
 
     if (emitInsIsLoadOrStore(ins))
     {
         if (emitInsIsLoad(ins))
         {
             result.insMemoryAccessKind =
                 emitInsIsStore(ins) ? PerfScoreMemoryAccessKind::ReadWrite : PerfScoreMemoryAccessKind::Read;
         }

@copilot Address this

jakobbotsch · 2026-04-20T22:45:07Z

@copilot Fix the formatting based on this patch:

diff --git a/src/coreclr/jit/emit.h b/src/coreclr/jit/emit.h
index 606a6c16..61c335a3 100644
--- a/src/coreclr/jit/emit.h
+++ b/src/coreclr/jit/emit.h
@@ -2205,42 +2205,42 @@ protected:
 #define PERFSCORE_LATENCY_WR_STACK         PERFSCORE_LATENCY_1C
 #define PERFSCORE_LATENCY_RD_WR_STACK      PERFSCORE_LATENCY_3C
 
 // a read, write or modify from constant location, possible def to use latency from L0 cache
 #define PERFSCORE_LATENCY_RD_CONST_ADDR    PERFSCORE_LATENCY_3C
 #define PERFSCORE_LATENCY_WR_CONST_ADDR    PERFSCORE_LATENCY_1C
 #define PERFSCORE_LATENCY_RD_WR_CONST_ADDR PERFSCORE_LATENCY_3C
 
 // a read, write or modify from memory location, possible def to use latency from L0 or L1 cache
 // plus an extra cost  (of 1.0) for a increased chance  of a cache miss
 #define PERFSCORE_LATENCY_RD_GENERAL       PERFSCORE_LATENCY_4C
 #define PERFSCORE_LATENCY_WR_GENERAL       PERFSCORE_LATENCY_1C
 #define PERFSCORE_LATENCY_RD_WR_GENERAL    PERFSCORE_LATENCY_4C
 
 #else
 #error Unknown TARGET
 #endif
 
     struct insExecutionCharacteristics
     {
-        float    insThroughput;
-        float    insLatency;
+        float                     insThroughput;
+        float                     insLatency;
         PerfScoreMemoryAccessKind insMemoryAccessKind;
     };
 
     float insEvaluateExecutionCost(instrDesc* id);
 
     insExecutionCharacteristics getInsExecutionCharacteristics(instrDesc* id);
 
     void perfScoreUnhandledInstruction(instrDesc* id, insExecutionCharacteristics* result);
 
 #endif // defined(DEBUG) || defined(LATE_DISASM)
 
     weight_t getCurrentBlockWeight();
 
     void dispIns(instrDesc* id);
 
     void appendToCurIG(instrDesc* id);
 
     /********************************************************************************************/
 
     struct instrDescJmp : instrDesc
diff --git a/src/coreclr/jit/emitloongarch64.cpp b/src/coreclr/jit/emitloongarch64.cpp
index 411d1505..311f84fd 100644
--- a/src/coreclr/jit/emitloongarch64.cpp
+++ b/src/coreclr/jit/emitloongarch64.cpp
@@ -5255,42 +5255,42 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
         { // xor + bnez/beqz or bnez/beqz + pcaddi + jirl
             assert((CombinedInsCnt == 2) || (CombinedInsCnt == 3));
             result.insLatency    = (CombinedInsCnt == 2) ? PERFSCORE_LATENCY_2C : PERFSCORE_LATENCY_3C;
             result.insThroughput = (CombinedInsCnt == 2) ? 5.5f : PERFSCORE_THROUGHPUT_5C;
         }
         else if (id->idInsOpt() == INS_OPTS_I)
         { // addi.d, srli.d, lu12i.w, ori, lu32i.d, lu52i.d
             result.insLatency    = PERFSCORE_LATENCY_1C * CombinedInsCnt;
             result.insThroughput = (CombinedInsCnt < 3)
                                        ? PERFSCORE_THROUGHPUT_4C * CombinedInsCnt
                                        : PERFSCORE_THROUGHPUT_4C * (CombinedInsCnt - 1) + PERFSCORE_THROUGHPUT_1C;
         }
         else if (id->idInsOpt() == INS_OPTS_C)
         { // pcaddu18i + jirl or lu12i.w + ori + lu32i.d + jirl
             assert((CombinedInsCnt == 2) || (CombinedInsCnt == 4));
             result.insLatency    = (CombinedInsCnt == 2) ? PERFSCORE_LATENCY_2C : PERFSCORE_LATENCY_4C;
             result.insThroughput = (CombinedInsCnt == 2) ? 3.5f : 10.5f;
         }
         else if (id->idInsOpt() == INS_OPTS_RELOC)
         { // pcalau12i + (addi.d or ld.d)
-            result.insLatency          = id->idIsCnsReloc() ? PERFSCORE_LATENCY_2C : PERFSCORE_LATENCY_5C;
-            result.insThroughput       = id->idIsCnsReloc() ? PERFSCORE_THROUGHPUT_6C : PERFSCORE_THROUGHPUT_4C;
+            result.insLatency    = id->idIsCnsReloc() ? PERFSCORE_LATENCY_2C : PERFSCORE_LATENCY_5C;
+            result.insThroughput = id->idIsCnsReloc() ? PERFSCORE_THROUGHPUT_6C : PERFSCORE_THROUGHPUT_4C;
             result.insMemoryAccessKind =
                 id->idIsCnsReloc() ? PerfScoreMemoryAccessKind::None : PerfScoreMemoryAccessKind::Read;
         }
         else
         {
             perfScoreUnhandledInstruction(id, &result);
         }
 
         return result;
     }
 
     assert(ins != INS_lea);
 
     if (emitInsIsLoadOrStore(ins))
     {
         if (emitInsIsLoad(ins))
         {
             result.insMemoryAccessKind =
                 emitInsIsStore(ins) ? PerfScoreMemoryAccessKind::ReadWrite : PerfScoreMemoryAccessKind::Read;
         }

@copilot Fix the formatting based on this patch:

diff --git a/src/coreclr/jit/emit.h b/src/coreclr/jit/emit.h
index 606a6c16..61c335a3 100644
--- a/src/coreclr/jit/emit.h
+++ b/src/coreclr/jit/emit.h
@@ -2205,42 +2205,42 @@ protected:
 #define PERFSCORE_LATENCY_WR_STACK         PERFSCORE_LATENCY_1C
 #define PERFSCORE_LATENCY_RD_WR_STACK      PERFSCORE_LATENCY_3C
 
 // a read, write or modify from constant location, possible def to use latency from L0 cache
 #define PERFSCORE_LATENCY_RD_CONST_ADDR    PERFSCORE_LATENCY_3C
 #define PERFSCORE_LATENCY_WR_CONST_ADDR    PERFSCORE_LATENCY_1C
 #define PERFSCORE_LATENCY_RD_WR_CONST_ADDR PERFSCORE_LATENCY_3C
 
 // a read, write or modify from memory location, possible def to use latency from L0 or L1 cache
 // plus an extra cost  (of 1.0) for a increased chance  of a cache miss
 #define PERFSCORE_LATENCY_RD_GENERAL       PERFSCORE_LATENCY_4C
 #define PERFSCORE_LATENCY_WR_GENERAL       PERFSCORE_LATENCY_1C
 #define PERFSCORE_LATENCY_RD_WR_GENERAL    PERFSCORE_LATENCY_4C
 
 #else
 #error Unknown TARGET
 #endif
 
     struct insExecutionCharacteristics
     {
-        float    insThroughput;
-        float    insLatency;
+        float                     insThroughput;
+        float                     insLatency;
         PerfScoreMemoryAccessKind insMemoryAccessKind;
     };
 
     float insEvaluateExecutionCost(instrDesc* id);
 
     insExecutionCharacteristics getInsExecutionCharacteristics(instrDesc* id);
 
     void perfScoreUnhandledInstruction(instrDesc* id, insExecutionCharacteristics* result);
 
 #endif // defined(DEBUG) || defined(LATE_DISASM)
 
     weight_t getCurrentBlockWeight();
 
     void dispIns(instrDesc* id);
 
     void appendToCurIG(instrDesc* id);
 
     /********************************************************************************************/
 
     struct instrDescJmp : instrDesc
diff --git a/src/coreclr/jit/emitloongarch64.cpp b/src/coreclr/jit/emitloongarch64.cpp
index 411d1505..311f84fd 100644
--- a/src/coreclr/jit/emitloongarch64.cpp
+++ b/src/coreclr/jit/emitloongarch64.cpp
@@ -5255,42 +5255,42 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
         { // xor + bnez/beqz or bnez/beqz + pcaddi + jirl
             assert((CombinedInsCnt == 2) || (CombinedInsCnt == 3));
             result.insLatency    = (CombinedInsCnt == 2) ? PERFSCORE_LATENCY_2C : PERFSCORE_LATENCY_3C;
             result.insThroughput = (CombinedInsCnt == 2) ? 5.5f : PERFSCORE_THROUGHPUT_5C;
         }
         else if (id->idInsOpt() == INS_OPTS_I)
         { // addi.d, srli.d, lu12i.w, ori, lu32i.d, lu52i.d
             result.insLatency    = PERFSCORE_LATENCY_1C * CombinedInsCnt;
             result.insThroughput = (CombinedInsCnt < 3)
                                        ? PERFSCORE_THROUGHPUT_4C * CombinedInsCnt
                                        : PERFSCORE_THROUGHPUT_4C * (CombinedInsCnt - 1) + PERFSCORE_THROUGHPUT_1C;
         }
         else if (id->idInsOpt() == INS_OPTS_C)
         { // pcaddu18i + jirl or lu12i.w + ori + lu32i.d + jirl
             assert((CombinedInsCnt == 2) || (CombinedInsCnt == 4));
             result.insLatency    = (CombinedInsCnt == 2) ? PERFSCORE_LATENCY_2C : PERFSCORE_LATENCY_4C;
             result.insThroughput = (CombinedInsCnt == 2) ? 3.5f : 10.5f;
         }
         else if (id->idInsOpt() == INS_OPTS_RELOC)
         { // pcalau12i + (addi.d or ld.d)
-            result.insLatency          = id->idIsCnsReloc() ? PERFSCORE_LATENCY_2C : PERFSCORE_LATENCY_5C;
-            result.insThroughput       = id->idIsCnsReloc() ? PERFSCORE_THROUGHPUT_6C : PERFSCORE_THROUGHPUT_4C;
+            result.insLatency    = id->idIsCnsReloc() ? PERFSCORE_LATENCY_2C : PERFSCORE_LATENCY_5C;
+            result.insThroughput = id->idIsCnsReloc() ? PERFSCORE_THROUGHPUT_6C : PERFSCORE_THROUGHPUT_4C;
             result.insMemoryAccessKind =
                 id->idIsCnsReloc() ? PerfScoreMemoryAccessKind::None : PerfScoreMemoryAccessKind::Read;
         }
         else
         {
             perfScoreUnhandledInstruction(id, &result);
         }
 
         return result;
     }
 
     assert(ins != INS_lea);
 
     if (emitInsIsLoadOrStore(ins))
     {
         if (emitInsIsLoad(ins))
         {
             result.insMemoryAccessKind =
                 emitInsIsStore(ins) ? PerfScoreMemoryAccessKind::ReadWrite : PerfScoreMemoryAccessKind::Read;
         }

@copilot address this

Agent-Logs-Url: https://github.com/dotnet/runtime/sessions/66dee1cd-5604-410e-8a7c-3a2838bc13ac Co-authored-by: jakobbotsch <7887810+jakobbotsch@users.noreply.github.com>

Copilot · 2026-04-20T23:21:09Z

@copilot Fix the formatting based on this patch:
diff --git a/src/coreclr/jit/emit.h b/src/coreclr/jit/emit.h

...

Applied in f492e75. Formatting was updated exactly as requested in src/coreclr/jit/emit.h and src/coreclr/jit/emitloongarch64.cpp.

@copilot Fix the formatting based on this patch:

...

Addressed in f492e75 with the requested alignment/spacing updates in both files.

@copilot Fix the formatting based on this patch:

...

Done in f492e75. The formatting patch has been applied exactly to emit.h and emitloongarch64.cpp.

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Replace PERFSCORE_MEMORY macros with PerfScoreMemoryAccessKind enum

701c1fa

Agent-Logs-Url: https://github.com/dotnet/runtime/sessions/db453486-2627-4fce-8b98-e726643e4dac Co-authored-by: jakobbotsch <7887810+jakobbotsch@users.noreply.github.com>

Copilot AI assigned Copilot and jakobbotsch Apr 20, 2026

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Copilot started work on behalf of jakobbotsch April 20, 2026 22:45 View session

Fix jit formatting alignment in emit.h and emitloongarch64.cpp

f492e75

Agent-Logs-Url: https://github.com/dotnet/runtime/sessions/66dee1cd-5604-410e-8a7c-3a2838bc13ac Co-authored-by: jakobbotsch <7887810+jakobbotsch@users.noreply.github.com>

Copilot AI requested review from Copilot and removed request for Copilot April 20, 2026 23:20

Copilot finished work on behalf of jakobbotsch April 20, 2026 23:22

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Replace PERFSCORE_MEMORY_* macros with PerfScoreMemoryAccessKind enum class#127148

Replace PERFSCORE_MEMORY_* macros with PerfScoreMemoryAccessKind enum class#127148
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copilot/replace-perfscore-memory-macros

Copilot AI commented Apr 20, 2026 •

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Copilot AI commented Apr 20, 2026 •

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Copilot AI commented Apr 20, 2026 •

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Copilot AI commented Apr 20, 2026 •

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