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Extend System.Runtime.Intrinsics.Arm to support nint and nuint (ArmBase + Crc32) #127327

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Extend System.Runtime.Intrinsics.Arm to support nint and nuint (ArmBase + Crc32) #127327

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Initial plan
Copilot Apr 23, 2026
6f34511
Add ArmBase/Crc32 nint/nuint APIs and refactor GenTreeHWIntrinsic aux…
Copilot Apr 23, 2026
7d5d081
Extend ArmBase/Crc32 hwintrinsic list entries with 64-bit instruction…
Copilot Apr 23, 2026
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7 changes: 0 additions & 7 deletions src/coreclr/jit/compiler.h
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Original file line number Diff line number Diff line change
Expand Up @@ -9789,13 +9789,6 @@ class Compiler
return getBaseTypeAndSizeOfSIMDType(typeHnd, nullptr);
}

CorInfoType getBaseJitTypeAndSizeOfSIMDType(CORINFO_CLASS_HANDLE typeHnd, unsigned* sizeBytes = nullptr);

CorInfoType getBaseJitTypeOfSIMDType(CORINFO_CLASS_HANDLE typeHnd)
{
return getBaseJitTypeAndSizeOfSIMDType(typeHnd, nullptr);
}

GenTree* impSIMDPopStack();

void setLclRelatedToSIMDIntrinsic(GenTree* tree);
Expand Down
24 changes: 6 additions & 18 deletions src/coreclr/jit/gentree.cpp
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Expand Up @@ -11171,7 +11171,7 @@ GenTree* Compiler::gtCloneExpr(GenTree* tree)
GenTreeHWIntrinsic(tree->TypeGet(), IntrinsicNodeBuilder(getAllocator(CMK_ASTNode), tree->AsMultiOp()),
tree->AsHWIntrinsic()->GetHWIntrinsicId(), tree->AsHWIntrinsic()->GetSimdBaseType(),
tree->AsHWIntrinsic()->GetSimdSize());
copy->AsHWIntrinsic()->SetAuxiliaryJitType(tree->AsHWIntrinsic()->GetAuxiliaryJitType());
copy->AsHWIntrinsic()->SetAuxiliaryType(tree->AsHWIntrinsic()->GetAuxiliaryType());

if (tree->AsHWIntrinsic()->IsUserCall())
{
Expand Down Expand Up @@ -21524,17 +21524,6 @@ void GenTreeJitIntrinsic::SetMethodHandle(Compiler* com
#endif // FEATURE_READYTORUN
}

var_types GenTreeJitIntrinsic::GetAuxiliaryType() const
{
CorInfoType auxiliaryJitType = GetAuxiliaryJitType();

if (auxiliaryJitType == CORINFO_TYPE_UNDEF)
{
return TYP_UNKNOWN;
}
return JitType2PreciseVarType(auxiliaryJitType);
}

var_types GenTreeJitIntrinsic::GetSimdBaseType() const
{
return (var_types)gtSimdBaseType;
Expand Down Expand Up @@ -29497,13 +29486,13 @@ bool GenTreeHWIntrinsic::OperIsMemoryLoad(GenTree** pAddr) const
case NI_AVX2_ConvertToVector256Int16:
case NI_AVX2_ConvertToVector256Int32:
case NI_AVX2_ConvertToVector256Int64:
if (GetAuxiliaryJitType() == CORINFO_TYPE_PTR)
if (GetAuxiliaryType() == TYP_U_IMPL)
{
addr = Op(1);
}
else
{
assert(GetAuxiliaryJitType() == CORINFO_TYPE_UNDEF);
assert(GetAuxiliaryType() == TYP_UNKNOWN);
}
break;

Expand Down Expand Up @@ -33855,14 +33844,13 @@ GenTree* Compiler::gtFoldExprHWIntrinsic(GenTreeHWIntrinsic* tree)
}
}
#elif defined(TARGET_ARM64)
CorInfoType auxJitType = tree->GetAuxiliaryJitType();
if (auxJitType != CORINFO_TYPE_UNDEF &&
genTypeSize(JITtype2varType(auxJitType)) != genTypeSize(simdBaseType))
var_types auxType = tree->GetAuxiliaryType();
if (auxType != TYP_UNKNOWN && genTypeSize(auxType) != genTypeSize(simdBaseType))
{
// Handle the "wide elements" variant of shift, where otherNode is a vector of ulongs,
// which is looped over to read the shift values. The values can safely be narrowed
// to the result type.
assert(auxJitType == CORINFO_TYPE_ULONG);
assert(auxType == TYP_ULONG);
assert(tree->TypeIs(TYP_SIMD16));

simd16_t result = {};
Expand Down
18 changes: 8 additions & 10 deletions src/coreclr/jit/gentree.h
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Expand Up @@ -6415,7 +6415,7 @@ struct GenTreeJitIntrinsic : public GenTreeMultiOp
};
regNumberSmall gtOtherReg; // The second register for multi-reg intrinsics.
MultiRegSpillFlags gtSpillFlags; // Spill flags for multi-reg intrinsics.
unsigned char gtAuxiliaryJitType; // For intrinsics than need another type (e.g. Avx2.Gather* or SIMD (by element))
unsigned char gtAuxiliaryType; // For intrinsics than need another type (e.g. Avx2.Gather* or SIMD (by element))
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unsigned char gtSimdBaseType; // SIMD vector base JIT type
unsigned char gtSimdSize; // SIMD vector size in bytes, use 0 for scalar intrinsics
NamedIntrinsic gtHWIntrinsicId;
Expand Down Expand Up @@ -6509,19 +6509,17 @@ struct GenTreeJitIntrinsic : public GenTreeMultiOp
gtSpillFlags = SetMultiRegSpillFlagsByIdx(gtSpillFlags, flags, idx);
}

CorInfoType GetAuxiliaryJitType() const
var_types GetAuxiliaryType() const
{
return (CorInfoType)gtAuxiliaryJitType;
return (var_types)gtAuxiliaryType;
}

void SetAuxiliaryJitType(CorInfoType auxiliaryJitType)
void SetAuxiliaryType(var_types auxiliaryType)
{
gtAuxiliaryJitType = (unsigned char)auxiliaryJitType;
assert(gtAuxiliaryJitType == auxiliaryJitType);
gtAuxiliaryType = (unsigned char)auxiliaryType;
assert(gtAuxiliaryType == auxiliaryType);
}

var_types GetAuxiliaryType() const;

// The invariant here is that simdBaseType is a converted
// CorInfoType using JitType2PreciseVarType.
void SetSimdBaseType(var_types simdBaseType)
Expand Down Expand Up @@ -6555,7 +6553,7 @@ struct GenTreeJitIntrinsic : public GenTreeMultiOp
: GenTreeMultiOp(oper, type, allocator, gtInlineOperands DEBUGARG(false), operands...)
, gtOtherReg(REG_NA)
, gtSpillFlags(0)
, gtAuxiliaryJitType(CORINFO_TYPE_UNDEF)
, gtAuxiliaryType(TYP_UNKNOWN)
, gtSimdBaseType((unsigned char)simdBaseType)
, gtSimdSize((unsigned char)simdSize)
, gtHWIntrinsicId(NI_Illegal)
Expand All @@ -6581,7 +6579,7 @@ struct GenTreeJitIntrinsic : public GenTreeMultiOp
gtInlineOperands DEBUGARG(false))
, gtOtherReg(REG_NA)
, gtSpillFlags(0)
, gtAuxiliaryJitType(CORINFO_TYPE_UNDEF)
, gtAuxiliaryType(TYP_UNKNOWN)
, gtSimdBaseType((unsigned char)simdBaseType)
, gtSimdSize((unsigned char)simdSize)
, gtHWIntrinsicId(NI_Illegal)
Expand Down
26 changes: 13 additions & 13 deletions src/coreclr/jit/hwintrinsic.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2344,15 +2344,15 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
// We want to be able to differentiate between them so lets
// just track the aux type as a ptr or undefined, depending

CorInfoType auxiliaryType = CORINFO_TYPE_UNDEF;
var_types auxiliaryType = TYP_UNKNOWN;

if (!varTypeIsSIMD(op1))
{
auxiliaryType = CORINFO_TYPE_PTR;
auxiliaryType = TYP_U_IMPL;
retNode->gtFlags |= (GTF_EXCEPT | GTF_GLOB_REF);
}

retNode->AsHWIntrinsic()->SetAuxiliaryJitType(auxiliaryType);
retNode->AsHWIntrinsic()->SetAuxiliaryType(auxiliaryType);
break;
}

Expand All @@ -2372,7 +2372,7 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
case NI_Sve_ConvertToUInt64:
// Save the base type of return SIMD. It is used to contain this intrinsic inside
// ConditionalSelect.
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(getBaseJitTypeOfSIMDType(sig->retTypeSigClass));
retNode->AsHWIntrinsic()->SetAuxiliaryType(getBaseTypeOfSIMDType(sig->retTypeSigClass));
break;
default:
break;
Expand Down Expand Up @@ -2407,12 +2407,12 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
case NI_AdvSimd_AddWideningUpper:
case NI_AdvSimd_SubtractWideningUpper:
assert(varTypeIsSIMD(op1->TypeGet()));
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(getBaseJitTypeOfSIMDType(sigReader.op1ClsHnd));
retNode->AsHWIntrinsic()->SetAuxiliaryType(getBaseTypeOfSIMDType(sigReader.op1ClsHnd));
break;

case NI_AdvSimd_Arm64_AddSaturateScalar:
assert(varTypeIsSIMD(op2->TypeGet()));
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(getBaseJitTypeOfSIMDType(sigReader.op2ClsHnd));
retNode->AsHWIntrinsic()->SetAuxiliaryType(getBaseTypeOfSIMDType(sigReader.op2ClsHnd));
break;

case NI_ArmBase_Arm64_MultiplyHigh:
Expand Down Expand Up @@ -2447,13 +2447,13 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
case NI_Sve_CreateWhileLessThanOrEqualMaskUInt16:
case NI_Sve_CreateWhileLessThanOrEqualMaskUInt32:
case NI_Sve_CreateWhileLessThanOrEqualMaskUInt64:
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(sigReader.op1JitType);
retNode->AsHWIntrinsic()->SetAuxiliaryType(JitType2PreciseVarType(sigReader.op1JitType));
break;

case NI_Sve_ShiftLeftLogical:
case NI_Sve_ShiftRightArithmetic:
case NI_Sve_ShiftRightLogical:
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(getBaseJitTypeOfSIMDType(sigReader.op2ClsHnd));
retNode->AsHWIntrinsic()->SetAuxiliaryType(getBaseTypeOfSIMDType(sigReader.op2ClsHnd));
break;

default:
Expand Down Expand Up @@ -2500,7 +2500,7 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
case NI_AVX2_GatherVector128:
case NI_AVX2_GatherVector256:
assert(varTypeIsSIMD(op2->TypeGet()));
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(getBaseJitTypeOfSIMDType(sigReader.op2ClsHnd));
retNode->AsHWIntrinsic()->SetAuxiliaryType(getBaseTypeOfSIMDType(sigReader.op2ClsHnd));
break;

#elif defined(TARGET_ARM64)
Expand Down Expand Up @@ -2543,8 +2543,8 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
assert(varTypeIsSIMD(op3->TypeGet()));
if (numArgs == 3)
{
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(
getBaseJitTypeOfSIMDType(sigReader.op3ClsHnd));
retNode->AsHWIntrinsic()->SetAuxiliaryType(
getBaseTypeOfSIMDType(sigReader.op3ClsHnd));
}
break;
#endif
Expand All @@ -2568,8 +2568,8 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
assert(varTypeIsSIMD(op3->TypeGet()));
if (numArgs == 4)
{
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(
getBaseJitTypeOfSIMDType(sigReader.op3ClsHnd));
retNode->AsHWIntrinsic()->SetAuxiliaryType(
getBaseTypeOfSIMDType(sigReader.op3ClsHnd));
}
break;
#endif
Expand Down
58 changes: 29 additions & 29 deletions src/coreclr/jit/hwintrinsicarm64.cpp
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Expand Up @@ -3179,7 +3179,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
CORINFO_ARG_LIST_HANDLE arg = sig->args;
arg = info.compCompHnd->getArgNext(arg);
CORINFO_CLASS_HANDLE argClass = info.compCompHnd->getArgClass(sig, arg);
CorInfoType ptrType = getBaseJitTypeOfSIMDType(argClass);
CorInfoType ptrType = CORINFO_TYPE_UNDEF;
CORINFO_CLASS_HANDLE tmpClass = NO_CLASS_HANDLE;

// The size of narrowed target elements is determined from the second argument of StoreNarrowing().
Expand All @@ -3195,7 +3195,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
op2 = impPopStack().val;
op1 = impPopStack().val;
retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, op3, intrinsic, simdBaseType, simdSize);
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(ptrType);
retNode->AsHWIntrinsic()->SetAuxiliaryType(JitType2PreciseVarType(ptrType));
break;
}

Expand Down Expand Up @@ -3266,7 +3266,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
op1 = impPopStack().val;

CorInfoType op1BaseJitType = getBaseJitTypeOfSIMDType(argClass);
var_types op1BaseType = getBaseTypeOfSIMDType(argClass);

// HWInstrinsic requires a mask for op2
if (!varTypeIsMask(op2))
Expand All @@ -3277,7 +3277,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, intrinsic, simdBaseType, simdSize);

retNode->AsHWIntrinsic()->SetSimdBaseType(simdBaseType);
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(op1BaseJitType);
retNode->AsHWIntrinsic()->SetAuxiliaryType(op1BaseType);
break;
}
case NI_Sve_GatherPrefetch8Bit:
Expand Down Expand Up @@ -3311,11 +3311,11 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
assert(HWIntrinsicInfo::isImmOp(intrinsic, op3));
op3 = addRangeCheckIfNeeded(intrinsic, op3, immLowerBound, immUpperBound);

argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
op2 = getArgForHWIntrinsic(argType, argClass);
CorInfoType op2BaseJitType = getBaseJitTypeOfSIMDType(argClass);
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
op1 = impPopStack().val;
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
op2 = getArgForHWIntrinsic(argType, argClass);
var_types op2BaseType = getBaseTypeOfSIMDType(argClass);
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
op1 = impPopStack().val;

#ifdef DEBUG

Expand All @@ -3330,7 +3330,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
}
#endif
retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, op3, intrinsic, simdBaseType, simdSize);
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(op2BaseJitType);
retNode->AsHWIntrinsic()->SetAuxiliaryType(op2BaseType);
}
else
{
Expand All @@ -3341,17 +3341,17 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
assert(HWIntrinsicInfo::isImmOp(intrinsic, op4));
op4 = addRangeCheckIfNeeded(intrinsic, op4, immLowerBound, immUpperBound);

argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg3, &argClass)));
op3 = getArgForHWIntrinsic(argType, argClass);
CorInfoType op3BaseJitType = getBaseJitTypeOfSIMDType(argClass);
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
op2 = getArgForHWIntrinsic(argType, argClass);
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
op1 = impPopStack().val;
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg3, &argClass)));
op3 = getArgForHWIntrinsic(argType, argClass);
var_types op3BaseType = getBaseTypeOfSIMDType(argClass);
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
op2 = getArgForHWIntrinsic(argType, argClass);
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
op1 = impPopStack().val;

assert(varTypeIsSIMD(op3->TypeGet()));
retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, op3, op4, intrinsic, simdBaseType, simdSize);
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(op3BaseJitType);
retNode->AsHWIntrinsic()->SetAuxiliaryType(op3BaseType);
}

break;
Expand Down Expand Up @@ -3468,7 +3468,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
var_types argType1 = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
var_types argType2 = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));

CorInfoType op1BaseJitType = getBaseJitTypeOfSIMDType(argClass);
var_types op1BaseType = getBaseTypeOfSIMDType(argClass);

op2 = impPopStack().val;
op1 = impPopStack().val;
Expand All @@ -3480,7 +3480,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
op1 = gtConvertTableOpToFieldList(op1, fieldCount);
}
retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, intrinsic, simdBaseType, simdSize);
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(op1BaseJitType);
retNode->AsHWIntrinsic()->SetAuxiliaryType(op1BaseType);
break;
}

Expand All @@ -3500,10 +3500,10 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
op2 = impPopStack().val;
op1 = impPopStack().val;

CorInfoType op1BaseJitType = getBaseJitTypeOfSIMDType(argClass);
retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, intrinsic, simdBaseType, simdSize);
var_types op1BaseType = getBaseTypeOfSIMDType(argClass);
retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, intrinsic, simdBaseType, simdSize);
retNode->AsHWIntrinsic()->SetSimdBaseType(simdBaseType);
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(op1BaseJitType);
retNode->AsHWIntrinsic()->SetAuxiliaryType(op1BaseType);
break;
}

Expand All @@ -3516,18 +3516,18 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
CORINFO_ARG_LIST_HANDLE arg2 = info.compCompHnd->getArgNext(arg1);
CORINFO_CLASS_HANDLE argClass = NO_CLASS_HANDLE;

var_types argType1 = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
CorInfoType op1BaseJitType = getBaseJitTypeOfSIMDType(argClass);
var_types argType2 = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
CorInfoType op2BaseJitType = getBaseJitTypeOfSIMDType(argClass);
assert(JitType2PreciseVarType(op1BaseJitType) == simdBaseType);
var_types argType1 = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
var_types op1BaseType = getBaseTypeOfSIMDType(argClass);
var_types argType2 = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
var_types op2BaseType = getBaseTypeOfSIMDType(argClass);
assert(op1BaseType == simdBaseType);

op2 = impPopStack().val;
op1 = impPopStack().val;

retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, intrinsic, simdBaseType, simdSize);
retNode->AsHWIntrinsic()->SetSimdBaseType(simdBaseType);
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(op2BaseJitType);
retNode->AsHWIntrinsic()->SetAuxiliaryType(op2BaseType);
break;
}

Expand Down
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