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Remove regNumberSmall and just use regNumber everywhere #127542

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db0259f
Remove regNumberSmall
tannergooding Apr 29, 2026
f7c14df
Fix build and respond to PR feedback
tannergooding Apr 29, 2026
d33aa1d
Fix formatting
tannergooding Apr 29, 2026
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2 changes: 1 addition & 1 deletion src/coreclr/jit/abi.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -200,7 +200,7 @@ ABIPassingSegment ABIPassingSegment::InRegister(regNumber reg, unsigned offset,
{
assert(reg != REG_NA);
ABIPassingSegment segment;
segment.m_register = static_cast<regNumberSmall>(reg);
segment.m_register = static_cast<regNumber>(reg);
segment.m_stackOffset = 0;
segment.Offset = offset;
segment.Size = size;
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6 changes: 3 additions & 3 deletions src/coreclr/jit/abi.h
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Expand Up @@ -8,9 +8,9 @@ enum class WellKnownArg : unsigned;

class ABIPassingSegment
{
regNumberSmall m_register = REG_NA;
bool m_isFullStackSlot = true;
unsigned m_stackOffset = 0;
regNumber m_register = REG_NA;
bool m_isFullStackSlot = true;
unsigned m_stackOffset = 0;

public:
bool IsPassedInRegister() const;
Expand Down
8 changes: 4 additions & 4 deletions src/coreclr/jit/clrjit.natvis
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Expand Up @@ -205,10 +205,10 @@ Documentation for VS debugger format specifiers: https://learn.microsoft.com/vis
</Type>

<Type Name="emitter::instrDesc">
<DisplayString Condition="(_idInsFmt == IF_RRD) || (_idInsFmt == IF_RWR) || (_idInsFmt == IF_RRW)">{_idIns,en} {_idReg1,en}</DisplayString>
<DisplayString Condition="(_idInsFmt == IF_RRD_CNS) || (_idInsFmt == IF_RWR_CNS) || (_idInsFmt == IF_RRW_CNS)">{_idIns,en} {_idReg1,en}, {_idLargeCns,d}</DisplayString>
<DisplayString Condition="(_idInsFmt == IF_RRW_SHF) &amp;&amp; (_idLargeCns != 0)">{_idIns,en} {_idReg1,en}, {_idLargeCns,d}</DisplayString>
<DisplayString Condition="(_idInsFmt == IF_RRW_SHF) &amp;&amp; (_idLargeCns == 0)">{_idIns,en} {_idReg1,en}, {_idSmallCns,d}</DisplayString>
<DisplayString Condition="(_idInsFmt == IF_RRD) || (_idInsFmt == IF_RWR) || (_idInsFmt == IF_RRW)">{_idIns,en} {(regNumber)_idReg1,en}</DisplayString>
<DisplayString Condition="(_idInsFmt == IF_RRD_CNS) || (_idInsFmt == IF_RWR_CNS) || (_idInsFmt == IF_RRW_CNS)">{_idIns,en} {(regNumber)_idReg1,en}, {_idLargeCns,d}</DisplayString>
<DisplayString Condition="(_idInsFmt == IF_RRW_SHF) &amp;&amp; (_idLargeCns != 0)">{_idIns,en} {(regNumber)_idReg1,en}, {_idLargeCns,d}</DisplayString>
<DisplayString Condition="(_idInsFmt == IF_RRW_SHF) &amp;&amp; (_idLargeCns == 0)">{_idIns,en} {(regNumber)_idReg1,en}, {_idSmallCns,d}</DisplayString>
<DisplayString>{_idIns,en}</DisplayString>
</Type>

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22 changes: 11 additions & 11 deletions src/coreclr/jit/compiler.h
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Expand Up @@ -771,16 +771,16 @@ class LclVarDsc
#endif

private:
regNumberSmall _lvRegNum; // Used to store the register this variable is in (or, the low register of a
// register pair). It is set during codegen any time the
// variable is enregistered (lvRegister is only set
// to non-zero if the variable gets the same register assignment for its entire
// lifetime).
regNumber _lvRegNum; // Used to store the register this variable is in (or, the low register of a
// register pair). It is set during codegen any time the
// variable is enregistered (lvRegister is only set
// to non-zero if the variable gets the same register assignment for its entire
// lifetime).
#if !defined(TARGET_64BIT)
regNumberSmall _lvOtherReg; // Used for "upper half" of long var.
#endif // !defined(TARGET_64BIT)
regNumber _lvOtherReg; // Used for "upper half" of long var.
#endif // !defined(TARGET_64BIT)

regNumberSmall _lvArgInitReg; // the register into which the argument is moved at entry
regNumber _lvArgInitReg; // the register into which the argument is moved at entry

public:
// The register number is stored in a small format (8 bits), but the getters return and the setters take
Expand All @@ -795,7 +795,7 @@ class LclVarDsc

void SetRegNum(regNumber reg)
{
_lvRegNum = (regNumberSmall)reg;
_lvRegNum = (regNumber)reg;
assert(_lvRegNum == reg);
}

Expand Down Expand Up @@ -824,7 +824,7 @@ class LclVarDsc

void SetOtherReg(regNumber reg)
{
_lvOtherReg = (regNumberSmall)reg;
_lvOtherReg = reg;
assert(_lvOtherReg == reg);
}
#endif // !TARGET_64BIT
Expand Down Expand Up @@ -877,7 +877,7 @@ class LclVarDsc

void SetArgInitReg(regNumber reg)
{
_lvArgInitReg = (regNumberSmall)reg;
_lvArgInitReg = (regNumber)reg;
assert(_lvArgInitReg == reg);
}

Expand Down
4 changes: 1 addition & 3 deletions src/coreclr/jit/emit.cpp
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Expand Up @@ -3582,9 +3582,7 @@ emitter::instrDesc* emitter::emitNewInstrCallInd(int argCnt,
id->idSetIsCall();

#ifdef TARGET_XARCH
/* Store the displacement and make sure the value fit */
id->idAddr()->iiaAddrMode.amDisp = disp;
assert(id->idAddr()->iiaAddrMode.amDisp == disp);
id->idAddr()->iiaAddrMode.amDisp(disp);
#endif // TARGET_XARCH

/* Save the live GC registers in the unused register fields */
Expand Down
138 changes: 90 additions & 48 deletions src/coreclr/jit/emit.h
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Expand Up @@ -621,10 +621,52 @@ class emitter

struct emitAddrMode
{
regNumber amBaseReg : REGNUM_BITS + 1;
regNumber amIndxReg : REGNUM_BITS + 1;
emitter::opSize amScale : 2;
int amDisp : AM_DISP_BITS;
private:
unsigned _amBaseReg : REGNUM_BITS + 1;
unsigned _amIndxReg : REGNUM_BITS + 1;
emitter::opSize _amScale : 2;
int _amDisp : AM_DISP_BITS;

public:
regNumber amBaseReg() const
{
return static_cast<regNumber>(_amBaseReg);
}
void amBaseReg(regNumber reg)
{
_amBaseReg = static_cast<unsigned>(reg);
assert(reg == static_cast<regNumber>(_amBaseReg));
}

regNumber amIndxReg() const
{
return static_cast<regNumber>(_amIndxReg);
}
void amIndxReg(regNumber reg)
{
_amIndxReg = static_cast<unsigned>(reg);
assert(reg == static_cast<regNumber>(_amIndxReg));
}

emitter::opSize amScale() const
{
return static_cast<emitter::opSize>(_amScale);
}
void amScale(emitter::opSize scale)
{
_amScale = scale;
assert(scale == _amScale);
}

int amDisp() const
{
return _amDisp;
}
void amDisp(ssize_t disp)
{
_amDisp = static_cast<int>(disp);
assert(disp == _amDisp);
}
};

#endif // TARGET_XARCH
Expand Down Expand Up @@ -805,8 +847,8 @@ class emitter
// the live gcrefReg mask for the call instructions on x86/x64
//
#if !defined(TARGET_XARCH)
regNumber _idReg1 : REGNUM_BITS; // register num
regNumber _idReg2 : REGNUM_BITS;
unsigned _idReg1 : REGNUM_BITS; // register num
unsigned _idReg2 : REGNUM_BITS;
#endif

////////////////////////////////////////////////////////////////////////
Expand All @@ -832,8 +874,8 @@ class emitter
unsigned _idCustom2 : 1;
unsigned _idCustom3 : 1;
#if defined(TARGET_XARCH)
regNumber _idReg1 : REGNUM_BITS; // register num
regNumber _idReg2 : REGNUM_BITS;
unsigned _idReg1 : REGNUM_BITS; // register num
unsigned _idReg2 : REGNUM_BITS;
#endif

#define _idBound _idCustom1 /* jump target / frame offset bound */
Expand Down Expand Up @@ -1075,8 +1117,8 @@ class emitter
#ifdef TARGET_ARM
struct
{
regNumber _idReg3 : REGNUM_BITS;
regNumber _idReg4 : REGNUM_BITS;
unsigned _idReg3 : REGNUM_BITS;
unsigned _idReg4 : REGNUM_BITS;
};
#elif defined(TARGET_ARM64)
struct
Expand All @@ -1085,24 +1127,24 @@ class emitter
emitLclVarAddr iiaLclVar;
unsigned _idRegBit : 1; // Reg3 is scaled by idOpSize bits
GCtype _idGCref2 : 2;
regNumber _idReg3 : REGNUM_BITS;
regNumber _idReg4 : REGNUM_BITS;
unsigned _idReg3 : REGNUM_BITS;
unsigned _idReg4 : REGNUM_BITS;
};

insSvePattern _idSvePattern;

#elif defined(TARGET_XARCH)
struct
{
regNumber _idReg3 : REGNUM_BITS;
regNumber _idReg4 : REGNUM_BITS;
unsigned _idReg3 : REGNUM_BITS;
unsigned _idReg4 : REGNUM_BITS;
};
#elif defined(TARGET_LOONGARCH64)
struct
{
unsigned int iiaEncodedInstr; // instruction's binary encoding.
regNumber _idReg3 : REGNUM_BITS;
regNumber _idReg4 : REGNUM_BITS;
unsigned int _idReg3 : REGNUM_BITS;
unsigned int _idReg4 : REGNUM_BITS;
};

struct
Expand Down Expand Up @@ -1132,8 +1174,8 @@ class emitter
#elif defined(TARGET_RISCV64)
struct
{
regNumber _idReg3 : REGNUM_BITS;
regNumber _idReg4 : REGNUM_BITS;
unsigned int _idReg3 : REGNUM_BITS;
unsigned int _idReg4 : REGNUM_BITS;
unsigned int iiaEncodedInstr; // instruction's binary encoding.
};

Expand Down Expand Up @@ -1297,12 +1339,12 @@ class emitter

regNumber idReg1() const
{
return _idReg1;
return static_cast<regNumber>(_idReg1);
}
void idReg1(regNumber reg)
{
_idReg1 = reg;
assert(reg == _idReg1);
_idReg1 = static_cast<unsigned>(reg);
assert(reg == static_cast<regNumber>(_idReg1));
}

#ifdef TARGET_WASM
Expand Down Expand Up @@ -1332,37 +1374,37 @@ class emitter

regNumber idReg2() const
{
return _idReg2;
return static_cast<regNumber>(_idReg2);
}
void idReg2(regNumber reg)
{
_idReg2 = reg;
assert(reg == _idReg2);
_idReg2 = static_cast<unsigned>(reg);
assert(reg == static_cast<regNumber>(_idReg2));
}

#if defined(TARGET_XARCH)
regNumber idReg3() const
{
assert(!idIsSmallDsc());
return idAddr()->_idReg3;
return static_cast<regNumber>(idAddr()->_idReg3);
}
void idReg3(regNumber reg)
{
assert(!idIsSmallDsc());
idAddr()->_idReg3 = reg;
assert(reg == idAddr()->_idReg3);
idAddr()->_idReg3 = static_cast<unsigned>(reg);
assert(reg == static_cast<regNumber>(idAddr()->_idReg3));
}

regNumber idReg4() const
{
assert(!idIsSmallDsc());
return idAddr()->_idReg4;
return static_cast<regNumber>(idAddr()->_idReg4);
}
void idReg4(regNumber reg)
{
assert(!idIsSmallDsc());
idAddr()->_idReg4 = reg;
assert(reg == idAddr()->_idReg4);
idAddr()->_idReg4 = static_cast<unsigned>(reg);
assert(reg == static_cast<regNumber>(idAddr()->_idReg4));
}

bool idHasReg1() const
Expand Down Expand Up @@ -1511,24 +1553,24 @@ class emitter
regNumber idReg3() const
{
assert(!idIsSmallDsc());
return idAddr()->_idReg3;
return static_cast<regNumber>(idAddr()->_idReg3);
}
void idReg3(regNumber reg)
{
assert(!idIsSmallDsc());
idAddr()->_idReg3 = reg;
assert(reg == idAddr()->_idReg3);
idAddr()->_idReg3 = static_cast<unsigned>(reg);
assert(reg == static_cast<regNumber>(idAddr()->_idReg3));
}
regNumber idReg4() const
{
assert(!idIsSmallDsc());
return idAddr()->_idReg4;
return static_cast<regNumber>(idAddr()->_idReg4);
}
void idReg4(regNumber reg)
{
assert(!idIsSmallDsc());
idAddr()->_idReg4 = reg;
assert(reg == idAddr()->_idReg4);
idAddr()->_idReg4 = static_cast<unsigned>(reg);
assert(reg == static_cast<regNumber>(idAddr()->_idReg4));
}
#ifdef TARGET_ARM64
bool idReg3Scaled() const
Expand Down Expand Up @@ -1610,24 +1652,24 @@ class emitter
regNumber idReg3() const
{
assert(!idIsSmallDsc());
return idAddr()->_idReg3;
return static_cast<regNumber>(idAddr()->_idReg3);
}
void idReg3(regNumber reg)
{
assert(!idIsSmallDsc());
idAddr()->_idReg3 = reg;
assert(reg == idAddr()->_idReg3);
idAddr()->_idReg3 = static_cast<unsigned>(reg);
assert(reg == static_cast<regNumber>(idAddr()->_idReg3));
}
regNumber idReg4() const
{
assert(!idIsSmallDsc());
return idAddr()->_idReg4;
return static_cast<regNumber>(idAddr()->_idReg4);
}
void idReg4(regNumber reg)
{
assert(!idIsSmallDsc());
idAddr()->_idReg4 = reg;
assert(reg == idAddr()->_idReg4);
idAddr()->_idReg4 = static_cast<unsigned>(reg);
assert(reg == static_cast<regNumber>(idAddr()->_idReg4));
}

#endif // TARGET_LOONGARCH64
Expand All @@ -1646,24 +1688,24 @@ class emitter
regNumber idReg3() const
{
assert(!idIsSmallDsc());
return idAddr()->_idReg3;
return static_cast<regNumber>(idAddr()->_idReg3);
}
void idReg3(regNumber reg)
{
assert(!idIsSmallDsc());
idAddr()->_idReg3 = reg;
assert(reg == idAddr()->_idReg3);
idAddr()->_idReg3 = static_cast<unsigned>(reg);
assert(reg == static_cast<regNumber>(idAddr()->_idReg3));
}
regNumber idReg4() const
{
assert(!idIsSmallDsc());
return idAddr()->_idReg4;
return static_cast<regNumber>(idAddr()->_idReg4);
}
void idReg4(regNumber reg)
{
assert(!idIsSmallDsc());
idAddr()->_idReg4 = reg;
assert(reg == idAddr()->_idReg4);
idAddr()->_idReg4 = static_cast<unsigned>(reg);
assert(reg == static_cast<regNumber>(idAddr()->_idReg4));
}

#endif // TARGET_RISCV64
Expand Down
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