Cart Catalogue

Cart Catalogue

All 26 catalogued bankswitch schemes are implemented and wired into automatic detection — the catalogue is closed. Unlike an open-ended mapper list that grows as new commercial hardware ships, the Atari 2600's bankswitch scheme set is a small, closed, well-known catalogue, and Rusty2600 covers all of it. This is a genuinely different kind of "complete" than a console with a perpetually-open mapper-number registry — there is no larger number to chase here.

Why bankswitching exists

The 6507 exposes only a 4 KiB cartridge window ($1000..=$1FFF). Anything larger — and many "exactly 4 KiB plus extra RAM or a coprocessor" carts — bankswitches by hotspot addresses: a read or write to a magic address selects a bank, adds on-cart RAM, or drives a coprocessor.

The Board trait

Every scheme implements one trait:

trait Board {
    fn cpu_read(&mut self, addr: u16) -> u8;    // runs read-triggered hotspots too
    fn cpu_write(&mut self, addr: u16, val: u8); // write-triggered hotspots + on-cart RAM
    fn tier(&self) -> Tier;                       // the honesty marker
    fn tick(&mut self) {}                         // per-CPU-cycle coprocessor hook (default no-op)
    fn tick_coprocessor(&mut self) {}             // independently-clocked coprocessor (default no-op)
}

detect(rom: &[u8]) resolves the scheme from a closed enum over every implemented board (not a trait object, keeping no_std dispatch static) — size-unambiguous schemes resolve purely by length; same-size collisions (there are several) are broken by hotspot-pattern heuristics ported from Stella's own CartDetector.

The honesty gate

Tier { Core, Curated, BestEffort } is an honesty marker, not a behavioral one — runtime behavior is identical regardless of tier. Core/Curated boards are accuracy-gated: they're allowed to back the accuracy oracle. BestEffort boards can never do so — enforced structurally by a CI test (tests/mapper_tier_honesty.rs), not just documented. See Architecture-Decision-Records ADR 0003.

The full catalogue (26 schemes, 3 tiers)

Scheme	Size	Mechanism	RAM / coprocessor	Tier
2K	2 KiB	none (data repeats in the 4K window)	—	Core
4K	4 KiB	none (single bank)	—	Core
CV (Commavid)	2 KiB	fixed bank + on-cart RAM	+1 KiB RAM	Curated
F8	8 KiB	2×4K, hotspot select	—	Curated
F6	16 KiB	4×4K, hotspot select	—	Curated
F4	32 KiB	8×4K, hotspot select	—	Curated
FA / CBS RAM Plus	12 KiB	3×4K, hotspot select	+256 B RAM	Curated
F8SC / F6SC / F4SC (Superchip)	8/16/32 KiB	F-series + Superchip RAM	+128 B RAM	Curated
DPC (Pitfall II)	10 KiB ROM	F8-style hotspots + custom Display Processor Chip	coprocessor	Curated
F0	64 KiB	16×4K, incrementing hotspot	—	BestEffort
FE (Activision)	8 KiB	stack-frame snoop (JSR/RTS)	—	BestEffort
E0 (Parker Bros)	8 KiB	four independently-selected 1K slices	—	BestEffort
E7 (M-Network)	16 KiB	eight 2K banks	+2 KiB RAM	Curated
3F (Tigervision)	up to 512 KiB	bank-select accumulator store	—	BestEffort
3E (Tigervision + RAM)	var	RAM-bank / ROM-bank accumulator store	+RAM	BestEffort
UA (UA Ltd.)	8 KiB	address-only hotspots	—	BestEffort
0840 (EconoBank)	8 KiB	address-only hotspots	—	BestEffort
EF / EFSC	64 KiB	16×4K (+SC RAM)	optional RAM	BestEffort
BF / BFSC	256 KiB	64×4K (+SC RAM)	optional RAM	BestEffort
DF / DFSC	128 KiB	32×4K (+SC RAM)	optional RAM	BestEffort
SB (Superbank)	128–256 KiB	address-low-bits select	—	BestEffort
X07	64 KiB	custom hotspot family	—	BestEffort
4A50	up to 128 KiB	previous-access-gated state machine	+RAM	BestEffort
AR (Supercharger)	6 KiB RAM	tape-load protocol, 3×2K RAM banks	RAM-based	BestEffort
DPC+	var	Harmony/Melody ARM coprocessor	ARM coproc	BestEffort
CDF / CDFJ / CDFJ+	var	Harmony/Melody ARM coprocessor	ARM coproc	BestEffort

Tier totals: 2 Core, 8 Curated, 16 BestEffort — 26 schemes total.

Notable schemes

• DPC (Pitfall II) — David Crane's custom Display Processor Chip, the only commercial game to use it. Implemented as F8-style bankswitching plus a memory-mapped register file (8 data fetchers, a hardware RNG, graphics streaming), clocked on CPU access rather than an independent clock.
• DPC+ and the CDF family — modern Harmony/Melody cartridge formats backed by a real ARM7TDMI microcontroller running alongside the 6507. Rusty2600 includes a real Thumb-1 interpreter crate (rusty2600-thumb, no_std, zero dependencies on any other Rusty2600 crate) to run this ARM code faithfully, ported from Gopher2600's Go implementation. These are the deepest BestEffort schemes in the catalogue — genuinely coprocessor-level emulation, not a shortcut.
• AR / Supercharger — loads its program from an emulated cassette-tape protocol into 6 KiB of on-cart RAM rather than from ROM at all; Rusty2600 ports the "fast-load" (ROM-image) path, not the analog audio-decoding "sound-load" path (out of scope for a no_std crate).

See also

Architecture-Overview · Testing-Strategy · Architecture-Decision-Records