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Welcome to the RustySNES Wiki

RustySNES is a cycle-accurate Super Nintendo Entertainment System / Super Famicom emulator written in pure Rust. Following the lineage of its predecessor RustyNES, it targets the Mesen2 / ares / higan accuracy bar: a master-clock lockstep scheduler, a strictly-owned bus, and a deterministic audio resync model.

RustySNES is under active development. Rather than describe a future state as if it already exists, this wiki (and the project's own docs/STATUS.md) is written to clearly separate what's shipped and usable today from what's planned.

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What's shipped today

• A cycle-accurate 65C816 CPU, PPU1/PPU2 video, and SPC700 + S-DSP audio core, all driven by a single 21,477,270 Hz master-clock lockstep scheduler.
• The core coprocessor set: DSP-1, Super FX (GSU), and SA-1 (Core/Curated tier), plus DSP-2, DSP-4, ST010, CX4, OBC1, and S-DD1 (BestEffort tier, validated against real commercial ROMs).
• LoROM, HiROM, ExHiROM, and ExLoROM cartridge memory-map models.
• A playable native desktop frontend (winit + wgpu + cpal + egui): real ROMs boot with picture, sound, and keyboard/gamepad control.
• A versioned, deterministic save-state format, plus rewind and run-ahead built on top of it.
• PAL region auto-detection.

What's still planned

• The full in-browser WebAssembly demo (the deployed build currently compiles but is a bootstrap scaffold, not yet a playable UI).
• SPC7110 booting to real content, ST018, and standalone S-RTC.
• The post-v1.0.0 "Reach" features: Lua scripting + a debugger, rollback netplay, RetroAchievements, TAS movie recording, and (as a stretch tail) shaders/cheats/a Libretro core.

See Roadmap for exactly which release each planned item lands in.

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Why RustySNES?

• Reference-grade accuracy — a from-scratch core on the 21.477 MHz NTSC master clock with a lockstep scheduler for every chip; the CPU's variable-cycle (6/8/12) instruction timings and dot-accurate PPU/HDMA behavior are cycle-exact, not approximated.
• Determinism as a hard contract — the asynchronous SPC700/S-DSP audio processor stays coherent with the main CPU through an integer relative-time accumulator, with no floating point in the timing path. The same seed, ROM, and input sequence yield a bit-identical framebuffer and audio output — the foundation save-states, rewind, and (eventually) netplay rollback all build on.
• Honest accuracy tiering — every coprocessor/board is tiered Core / Curated / BestEffort (see Architecture-Decision-Records); nothing is silently degraded, and the wiki says so plainly when something isn't done yet.
• Safe, modular Rust — the chip stack is no_std + alloc with a one-directional workspace graph, making each component independently testable.

Wiki Navigation

Use the sidebar to navigate.

• New users should start with Getting-Started and Building-from-Source.
• Developers looking to understand the core engine should explore the Architecture-Overview and the deep-dives into the CPU-65C816, PPU-5C77-5C78, and APU-SPC700-SDSP.
• See how Cartridge-and-Coprocessors covers the memory-map models and the coprocessor tiering.
• Check Testing-Strategy to see how the accuracy oracle works.
• Roadmap and Deferred-Features lay out what's next and what's intentionally not done yet.