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RISC-V Chiplet SoC v2.0.1

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@ed766 ed766 released this 13 Aug 00:03

Validated GCC/ISS and privileged-architecture release.

Evidence highlights:

  • 70/70 stable regression and 60/60 functional bins
  • 85/85 compiled-firmware executions with 178/178 points and 94/94 crosses
  • 12/12 Spike differential programs and 45/45 ACT4/Sail architectural tests
  • 3/3 RV32 formal groups, 14/14 RTL mutations, and 5/5 external-oracle mutations
  • 26/26 low-power targets, 4/4 UVM smoke tests, and 4/4 integrated CDC ratios

The release workflow requires the pinned external validation tools. Results remain open-source pre-silicon evidence rather than RISC-V certification or commercial signoff.