Name		Name	Last commit message	Last commit date
CS-354		CS-354
3-stage-pipeline.v		3-stage-pipeline.v
README.md		README.md
a.out		a.out
alu.v		alu.v
base_components.v		base_components.v
branch_control.v		branch_control.v
compile-and-run.sh		compile-and-run.sh
data_memory.v		data_memory.v
instruction_memory.v		instruction_memory.v
main_control.v		main_control.v
proj1.v		proj1.v
proj2-attempt.v		proj2-attempt.v
proj2.v		proj2.v
proj2_emily.v		proj2_emily.v
proj3-attempt2.v		proj3-attempt2.v
proj4.v		proj4.v

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CS385 Semester Project: Building a mini MIPS machine

Sean Clifford and Erik Jenson

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Verilog Implementation of a 16 bit simplified MIPS Processor implemented at mostly gate level.

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