ESP32-C5 - TWAI / CAN FD Specification/Documentation - Maximum supported rate (IDFGH-16303)

[wezhunter]

Answers checklist.

• I have read the documentation ESP-IDF Programming Guide and the issue is not addressed there.
• I have updated my IDF branch (master or release) to the latest version and checked that the issue is present there.
• I have searched the issue tracker for a similar issue and not found a similar issue.

General issue report

Hi,
Apologies if this can be found elsewhere but I've spent quite a bit of time looking and have been unable to find a definitive answer.

Please could someone confirm what the maximum theoretical and/or tested CAN FD rate is supported/works on the newly released ESP32-C5?

The reason I ask...

ESP32-C5 public TRM states "36 Controller Area Network Flexible Data-Rate [to be added later] 39%" but unfortunately there's no section in the TRM for CAN.

Datasheet doesn't mention a maximum supported rate, it's primarily standards and features.

Understand that it's dependant on the CAN FD transceiver used but would still be good to understand it's maximum capabilities/limitations for future transceiver selection (e.g 5/8/10Mbps).

Also, any indication as to when the TRM might be updated to include the specifics around the newer generation TWAI (CAN FD) interfaces?

Thanks in advance!

[wanckl]

@wezhunter Thanks for report the issue, as you can see the version of datasheet and TRM is less than v1.0, so it not a full/final version, we are continuing on updating it.

For C5 TWAI, theoretical it could support to more than 10M, but yeah it also depends on good transceiver, so with a regular transceiver we had tested up to 4M.

[wezhunter]

@wancld Thanks for the quick response and your support.

Yeah fully understand this remains a work in progress after production release.

Theoretical 10Mbps+ was my suspicion too and so it's great to have a similar confirmation and is useful to know. As an example Nvidia Jetson boards support up-to 10Mbps CAN FD (15Mbps max).

There are a few 8Mpbs transceivers but are yet to test them, tested 5Mbps sustained across both TWAI interfaces fine here.

Thanks again

[ppisa]

Hello @wezhunter and @wanckl, more information about a CTU CAN FD IP core used on ESP32-C5 can be found at our pages https://canbus.pages.fel.cvut.cz/ . The version integrated to actual production lots is the CTU CAN FD IP core version 2.5.1 so the exact archived datasheet for this version is there https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/raw/2v5-lts/doc/pdf/Datasheet_for_version_2.5.1.pdf . The main page refers to the master branch, actually progression to 2.6 and 2.7 releases.

As for the controller digital design bit-rates limitations, they are documented in the sections 2.8.1 Bit rate till 2.8.7 Minimum bit time / Maximal bit rate. The design allows the ration between time-quanta and bit-time as low as 5. The strict design imposed limits for the bit-timing

• Sync_Seg + Prop_Seg + Phase_Seg1 > 2 minimal time quanta.
• Phase_Seg2 >= 2 minimal time quanta

The practical is at least 8 time quanta per bit-time for arbitration. The 5 time quanta per data phase bit transmission is possible. I have tested/experimented with the design synthesized for the Intel EP4CGX15 based DB4CGX15 PCIe board some years ago and if I remember well, I have achieved communication even at 20 Mbps for data phase with 100 MHz design clocks. But this is extreme and with transceiver and the cables unrealistic for the real usage.

There are more option for TWAIFD peripherals clocks selection on ESP32-C5 and each clock chain has programmable frequencies and I am not sure about limitations which has to be provided by somebody from Espressif. There are options XTAL_CLK and RC_FAST_CLK and digital part runs at APB_CLK.

The default which seems to be used as base is TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M.

For the CTU CAN FD IP HDL design limits, more information can provide main author @Blebowski.

So in theory, this should be enough for 10 Mbps arbitration and 16 Mbps data-rate in the CTU CAN FD core. But there would be some synchronization with I/O pin domain and if I read ESP32-C5 datasheet correctly, then there is only option to map CAN FD controller pins through HP GPIO Matrix and we have experienced some delays/problems with signals routing when we attempted to use SPI routed through IO matrix when we work on IEEE 802.3cg 10BASE−T1S for NuttX on ESP32-C6 with 20 Mbps+. Same SPI worked reliably when direct pin function has been used.

So it is question still what are practical limitations of CAN FD bitrates on ESP32-C5. But 1 Mbps should be no problem for arbitration and I expect limit for data-rate above 8 Mbps.

[wezhunter]

Thank you @ppisa for the excellently detailed information and insight. We will bear all of this in mind and add to our own internal wiki here. Simply excellent and very much appreciated. Thanks!

Once we commence testing higher speed CAN FD transceivers I will report back our test results to this closed issue purely as a means of future reference & benefit to others.

Best,
Wez

[ppisa]

Once we commence testing higher speed CAN FD transceivers I will report back our test results to this closed issue purely as a means of future reference & benefit to others.

I am quite curious to see some experiment results. I have two esp32-c5-devkitc-1 kits there but I would not expect to have much time to play with them. I need to wrap-up three GSoC project I mentor, the semester/teaching requires preparation and I have some NuttX STM32 work for satellite tests systems... So ESP32-C5 has to wait for some student or my spare time. But I want to include it in our long term CAN latency testing which I want to extend to RTEMS and NuttX one day.

As for high-speed CAN FD transceivers, you should consider to use CAN-FD transceivers with SIC (Signal Improvement Capability) feature.

By the way, if you want to use the CTU CAN FD manuals as supplement before ESP32-C5 reference manual is ready then I have verified next parameters used for ESP32-C5 silicon: rx_buffer_size = 128 (512 bytes), txt_buffer_count = 4, sup_filtA = true, sup_filtB = true, sup_filtC = true, sup_range = true, sup_test_registers = true, sup_traffic_ctrs = true, sup_parity = true

[ppisa]

@wezhunter Information for mine and may it be your curiosity, I have done some CTU CAN FD testing to check our NFS root boot booted Zynq based boards for education after upgrade to Linux PREEMP_RT 6.12.43 kernel. I have loaded some build from CTU CAN FD 2.5 branch (something around ESP32-C5 used version) and tested it between two cores on FPGA (ideal condition, no clock jitter, disturbances etc.) and it worked at 20 Mbps data rate (100 MHz system clock, documented limit 1/5) and 1 Mbps arbitration as expected/no problem even if more cores send messages at fully flooded line. When connected to external transceivers and piece of random (flat) cable with termination, then the last working value has been 6 Mbps. But it was far from optimal cable and transceivers on our Zynq MZ_APO kits are old ones, probably with 5 Mbps limit, without SIC etc. It has been with default sample points and setting from Linux kernel so there can be chance to get little more even with these slow transceivers.

So I believe that on ESP32-C5 with ideal interconnection 16 Mbps for 80 MHz base clock should work same way. With physical CAN transceiver 8 Mbps or may be even more with SIC should be achievable. I have already bought some DIP packaged transceivers (no SIC one in DIP) for wire-wrap experiment with ESP32-C5. Feedback from others with different transceivers would be welcomed.

[Oleg-Perevyshin]

Is CAN FD support only available on the ESP32-C5?
Are there plans to support it on other chips, such as the ESP32-S3?

[wanckl]

@Oleg-Perevyshin

For now it only on C5, It's supported by chip design, so impossible to support on other chips, thanks.