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Upstream synchronization [v0.20] #73
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The initial motivation for doing this is to remove the `used` flag in the TD. If we use this flag, we end up being required to read from TDs that the OHCI controller might be modifying (i.e. the OHCI controller logically owns the TD). This happens when we try to allocate a new, empty TD while the OHCI host controller is working on a transfer. Move the `used` flag to `gtd_extra_data_t`. This data is only used by the CPU, and the OHCI controller never accesses it. The existing allocation method for TDs does *not* put an empty TD onto each ED (i.e it does *not* do what is shown in Figure 5-6 of the OHCI specification). Instead, the NextTD field of the last TD is set to 0. The TailP field of the ED is also set to 0. This works in many cases. However, this implementation means that the CPU may end up trying to write to the NextTD field of an in-progress transfer while the OHCI host controller logically owns it. Change the implementation to use an empty TD, as suggested by the specification, for endpoints other than EP0. This avoids the above issue. It is not necessary to make the change for EP0 because only at most one TD can ever be pending at a time. The above change should also remove the need for the stall workaround. In the future, we want to modify the code to access EDs through an uncached mapping. Because uncached mappings are slow, we want to access EDs as little as possible. Currently, when a TD completes, we access an ED in order to figure out the device address and endpoint number of the TD which was completed. Because moving `used` to `gtd_extra_data_t` necessitates expanding it, we have enough room to also store the device address and endpoint number of the TD. This patch does so. With the above two changes, we no longer need to access an ED when a TD completes. Also remove the `index` field from TDs as it is no longer necessary.
This code is written very carefully to always use an uncached view of memory to read/write EDs. An uncached view must *always* be used, or else cache behavior can corrupt the ED. As part of this change, combine access into as few word-sized accesses as possible. This makes the code perform better. Doing this involves giving type names to the bitfields that make up the ED's data words.
Signed-off-by: HiFiPhile <admin@hifiphile.com>
Signed-off-by: HiFiPhile <admin@hifiphile.com>
Signed-off-by: HiFiPhile <admin@hifiphile.com>
Signed-off-by: HiFiPhile <admin@hifiphile.com>
Signed-off-by: HiFiPhile <admin@hifiphile.com>
Signed-off-by: Mengsk <admin@hifiphile.com>
Signed-off-by: Mengsk <admin@hifiphile.com>
Signed-off-by: HiFiPhile <admin@hifiphile.com>
Signed-off-by: HiFiPhile <admin@hifiphile.com>
Signed-off-by: Mengsk <admin@hifiphile.com>
Signed-off-by: Mengsk <admin@hifiphile.com>
Signed-off-by: HiFiPhile <admin@hifiphile.com>
Signed-off-by: HiFiPhile <admin@hifiphile.com>
All four of these examples immediately crashed on stack overflow when connected, at least on a FRDM_K64F board. In 46fd822 the default freertos stack size was increased, but _only_ for stm32? Perhaps either all platform examples need the default increased, rather than increasing the problem task stacks as is done here. Signed-off-by: Karl Palsson <karl.palsson@marel.com>
Signed-off-by: HiFiPhile <admin@hifiphile.com>
dwc2 requires manually toggle Even/Odd bit manually for ISO IN transfer, that's poses a problem when bInterval > 1 mainly for audio class, as the moment the transfer is scheduled, we don't know when the host will issue IN token (bInterval vs bRefresh schenanigans). Linux driver use NAK interrupt to detect when the host is sending IN token and toggle the Even/Odd bit accordingly based on the current frame number and bInterval. However on ST's stripped down DWC2 FS controller (e.g STM32F4, STM32F7), NAK interrupt is not supported, even it's marked as always present in DWC2 databook. NAK interrupt is only supported on HS controller with external PHY. Instead I schedule all ISO IN transfer for next frame, if the transfer failed, incomplete isochronous IN transfer interrupt will be triggered and we can relaunch the transfer. Signed-off-by: HiFiPhile <admin@hifiphile.com>
Signed-off-by: HiFiPhile <admin@hifiphile.com>
Signed-off-by: HiFiPhile <admin@hifiphile.com>
Signed-off-by: HiFiPhile <admin@hifiphile.com>
Signed-off-by: Mengsk <admin@hifiphile.com>
Signed-off-by: HiFiPhile <admin@hifiphile.com>
make dcd_edpt_iso_alloc/activate as default API for ISO endpoint
Fix link to Getting Started documentation
# Conflicts: # examples/device/dfu/src/usb_descriptors.c # examples/device/dfu_runtime/src/usb_descriptors.c # src/device/usbd_control.c # src/portable/synopsys/dwc2/dcd_dwc2.c
use uint8_t for dfu state and status to reduce size
dcd/dwc2: fix EP0 multi-packet transfer logic
dcd/dwc2: support ISO IN transfer when bInterval > 1
osal/none: add nested count to spin lock
host/dwc2: cleanup transfer on device close
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
fix more alerts
release 0.20.0
update changelog.rst
This was referenced Nov 26, 2025
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Description
Update to
v0.20.0.Changes include pure tag
0.20.0merged on top of the branchrelease/v0.19(with partial limitation fix from #69).Notes
As the release "v0.19.0~2" wasn't pulblished yet, this changes will take place over the stable releasePublished 24.11.2025v0.18.0~6.The merging logic:
release/v0.20from therelease/v0.19, tagv0.19.0.20.20.0from the upstreamrelease/v0.20(this PR)Limitations
Blocking
stdio.hforsnprintf()isn't included whenCFG_TUSB_DEBUG_PRINTFis defined (fix(tusb_debug): Added stdio.h include when CFG_TUSB_DEBUG_PRINTF [WIP] #74)dcd_deinit()WEAK function returns false by default. Causes an assert intud_deinit(rhport)because of theTU_VERIFY(dcd_deinit(rhport));, (change(usbd): Changed return value to true for weak dcd_deinit() (quick fix) hathach/tinyusb#3370)Non-blocking
dcd_deinit()indcd_dwc2.c. For us, it is not critical, as we reconfigure the controller during the nextdcd_init(). (feature(dcd_dwc2): Added the dcd_deinit() stub call to avoid assert [WIP] #75)E (7258) cache: esp_cache_msync(116): start address: 0x4ff2eb07, or the size: 0x40 is(are) not aligned with cache line size (0x40)BAdditional notes
Conflicts, found during merging with
0.20.0:tusb_common.h:dcd_dwc2.c: