Add HSP clock and reset generator

Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml

@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/eswin,eic7700-hspcrg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ESWIN EIC7700 HSP Clock and Reset Generator
+
+maintainers:
+  - Xuyang Dong <dongxuyang@eswincomputing.com>
+
+description:
+  Clock and reset generator for the ESWIN EIC7700 HSP (high-speed peripherals).
+
+properties:
+  compatible:
+    const: eswin,eic7700-hspcrg
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: External 24MHz Oscillator clock
+      - description: HSP AXI top clock
+      - description: HSP configuration top clock
+      - description: MMC top clock
+      - description: SATA top clock
+
+  clock-names:
+    items:
+      - const: xtal24m
+      - const: axi
+      - const: cfg
+      - const: mmc
+      - const: sata
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/eswin,eic7700-hspcrg.h> for valid indices.
+
+  '#reset-cells':
+    const: 1
+    description:
+      See <dt-bindings/reset/eswin,eic7700-hspcrg.h> for valid indices.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@50440000 {
+        compatible = "eswin,eic7700-hspcrg";
+        reg = <0x50440000 0x2000>;
+        clocks = <&xtal24m>, <&clock 186>, <&clock 171>, <&clock 254>,
+                 <&clock 187>;
+        clock-names = "xtal24m", "axi", "cfg", "mmc", "sata";
+        #clock-cells = <1>;
+        #reset-cells = <1>;
+    };

arch/riscv/boot/dts/eswin/eic7700.dtsi

@@ -261,12 +261,6 @@
 				<&cpu3_intc 3>, <&cpu3_intc 7>;
 		};
 
-		hsp_sp_csr: hsp-sp-top-csr@0x50440000 {
-				compatible = "syscon";
-				#size-cells = <2>;
-				reg = <0x0 0x50440000 0x0 0x2000>;
-		};
-
 		clk: clock-controller@51828000 {
 			compatible = "eswin,eic7700-clock";
 			reg = <0x0 0x51828000 0x0 0x300>;
@@ -282,6 +276,24 @@
 			status = "disable";
 		};
 
+		hsp_sp_csr: hsp-sp-top-csr@0x50440000 {
+			compatible = "simple-bus", "syscon";
+			reg = <0x0 0x50440000 0x0 0x2000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			hspcrg: clock-controller@50440000 {
+				compatible = "eswin,eic7700-hspcrg";
+				reg = <0x0 0x50440000 0x0 0x2000>;
+				clocks = <&xtal24m>, <&clk 186>, <&clk 171>,
+					<&clk 254>, <&clk 187>;
+				clock-names = "xtal24m", "axi", "cfg", "mmc", "sata";
+				#clock-cells = <1>;
+				#reset-cells = <1>;
+			};
+		};
+
 		sata_phy: sata-phy@50440300 {
 			compatible = "eswin,eic7700-sata-phy";
 			reg = <0x0 0x50440300 0x0 0x40>;

drivers/clk/eswin/Kconfig

@@ -13,3 +13,16 @@ config COMMON_CLK_EIC7700
 	  SoC. The clock controller can generates and supplies clock to various
 	  peripherals within the SoC.
 	  Say yes here to support the clock controller on the EIC7700 SoC.
+
+config COMMON_CLK_EIC7700_HSP
+	tristate "EIC7700 HSP Clock Driver"
+	depends on ARCH_ESWIN || COMPILE_TEST
+	select AUXILIARY_BUS
+	select COMMON_CLK_EIC7700
+	select RESET_EIC7700_HSP if RESET_CONTROLLER
+	default ARCH_ESWIN
+	help
+	  This driver provides support for clock controller on ESWIN EIC7700
+	  HSP. The clock controller generates and supplies clocks to high
+	  speed peripherals within the SoC.
+	  Say yes here to support the clock controller on the EIC7700 HSP.

drivers/clk/eswin/Makefile

@@ -6,3 +6,4 @@
 obj-$(CONFIG_COMMON_CLK_ESWIN)		+= clk.o
 
 obj-$(CONFIG_COMMON_CLK_EIC7700)	+= clk-eic7700.o
+obj-$(CONFIG_COMMON_CLK_EIC7700_HSP)	+= clk-eic7700-hsp.o