edge-cores v0.1 - PyTorch to Custom ASICs MVP

v0.1 is the first working release of edge-cores, demonstrating an end-to-end path from PyTorch models to bare-metal C++ running on custom ASIC RTL.

The goal of this release is simple: make the whole flow work.

PyTorch model
    ↓
torch.export
    ↓
NNC
    ↓
bare-metal C++
    ↓
Clang / LLVM
    ↓
RV64 ELF
    ↓
custom ASIC RTL

What's included

• End-to-end PyTorch → C++ → ASIC RTL flow
• PyTorch graph export and lowering through NNC
• Generated bare-metal C++ inference code
• Standard Clang/LLVM-based build flow
• edge-rv and edge-rv-lite control planes for custom accelerators
• Verilator-based RTL execution and verification
• Llama 3 transformer block demo
• Reduced Qwen 3.6 decoder layer demo
• Minimal PyTorch SiLU end-to-end smoke test
• C++ examples for Tensor, DMA, activation, comparison, and synchronization
• edge_intrinsic.hpp as a reference software interface between C++ and custom ASIC instructions

Bring Your Own ASIC

The included edge-e3 NPU is a working reference implementation, but it is not required.

You can connect your own accelerator to edge-rv or edge-rv-lite and expose its operations through a C++ intrinsic interface following the edge_intrinsic.hpp example.

The intended flow is:

your PyTorch model
        ↓
       NNC
        ↓
generated / handwritten C++
        ↓
your intrinsic.hpp
        ↓
your custom instructions
        ↓
your ASIC

This allows a custom ASIC to participate in the same PyTorch-to-hardware workflow without requiring a custom LLVM backend or a dedicated compiler stack.

Status

v0.1 is an early MVP.

The focus of this release is not API stability or complete model coverage. It establishes a working software and hardware integration path that can already be used to demonstrate models, write hardware-aware C++ kernels, and bring up custom accelerators.

The path works. Now you can plug in your own ASIC.

What's next — v0.2

v0.1 makes the PyTorch → C++ → ASIC path work.

For v0.2, we're taking the next step: from working RTL to physical implementation.

The current edge-rv and edge-rv-lite reference cores will be replaced by edge-32, a new RV32-based architecture designed as the foundation of the edge-cores hardware stack.

Our target for v0.2:

PyTorch
   ↓
C++
   ↓
edge-32 / custom accelerators
   ↓
RTL
   ↓
ASAP7 synthesis & place-and-route

The goal is to provide not only RTL that simulates, but a complete reference design that can go through a real ASIC implementation flow.

v0.1 makes it run.
v0.2 makes it physical.