edge-cores v0.2 — Edge32 and physical design progress

v0.2 replaces the edge-rv control core used by the v0.1 E3 system with Edge32, a four-stage RV32 processor designed for NPU control and physical timing. The public PyTorch → bare-metal C++ → Verilator flow now runs on Edge32 with the encrypted Edge E3 RTL.

What changed

• Edge32 is the new public control core. Its RV32IMF pipeline, register file, and arithmetic units replace the former RV64 scalar path.
• The E3 software and simulation flow has moved to RV32. The public edge-e3enc composition runs the hello, Tensor, and PyTorch-to-NNC examples.
• Tensor control timing more closely reflects hardware latency. The maintained 64×64×128 BF16 Tensor example measures 8,753 cycles, or 93.59% effective MAC utilization. Cycle counts have shifted slightly as the timing model improved, with little effect on this workload's utilization.

E3 whole-system resource comparison

The matched synthesis comparison is v0.1 edge-rv@e3 versus v0.2 edge32@e3. Both were synthesized with Yosys 0.67+post for Xilinx xc7, using the same options and default DSP mapping.

E3 system resource	v0.1 edge-rv@e3	v0.2 edge32@e3	Change
Total cells	284,862	191,992	−32.6%
LUT1–LUT6	171,193	109,772	−35.9%
Flip-flops	43,332	38,516	−11.1%
CARRY4	8,420	6,512	−22.7%
MUXF7 + MUXF8	21,615	12,639	−41.5%
DSP48E1	101	93	−7.9%
RAMB18E1 / RAMB36E1	32 / 38	32 / 37	0 / −1

These are FPGA synthesis resource counts, not post-route ASIC area. The comparison covers the complete E3 system, so its savings include changes beyond the RV64-to-RV32 processor replacement. The separate cached-core comparison and its methodology are documented in the Edge32 README.

Physical implementation status

Routing has been completed for the following individual modules:

Design	Routed modules
Edge32	RV32 core, mul/div, GPR, FMAC, FDIV, FSQRT, and other scalar modules
Edge E3	ACTU

Routing is in progress for DTCM, the Tensor dot8/dot16 kernels, and WLD. FPR, CMPU, and DMA have not yet been routed. Full-core global routing remains in progress; v0.2 does not claim final chip-level routing or timing signoff.

v0.2 is a step from the working RTL flow established in v0.1 toward a physical implementation, with a smaller synthesized E3 system and measured progress at the module level.