Initial status register and access protection infrastructure#28
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fid0did0 wants to merge 6 commits intoflashrom:stagingfrom
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Initial status register and access protection infrastructure#28fid0did0 wants to merge 6 commits intoflashrom:stagingfrom
fid0did0 wants to merge 6 commits intoflashrom:stagingfrom
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- Read and write multiple status registers - Read is straightforward and most chips share same opcodes for RDSR1, RDS2 and RDSR3 - For chips with 2 status registers, WRSR takes either 1 or 2 bytes. When only 1 byte is supplied (which was the preious behaviour), the 2nd status register is cleared. (Our code automatically takes care of this.) - For chips with 3 status registers, each register is separately written to and we have many chips sharing opcodes for WRSR1, WRSR2 and WRSR3 - Get, set or prettyprint write protection mode for status register(s). Functionality exposed through struct status_register member. - This is controlled by SRP/SRWD or SRP0/SRP1 bit(s). Chips with SRP0 and SRP1 will most likely have at least 2 status registers. - For chips with SRP/SRWD bit, we can get/set SOFTWARE (status register unlocked) or HARDWARE (status register locked/unlocked subject to WP#) protection modes. - For chips with SRP0 and SRP1, we can additionally get/set POWER_CYCLE (status registers locked until next power down-up cycle) or PERMANENT modes. - We can also automatically detect how WP# affects the HARDWARE write protection mode. - struct flashchip contains pointer to a struct status_register (for allowing flexibility of reuse), which in turn has members to represent layout of status register(s) and, pointers to functions to read, write, print, set_wp_mode, get_wp_mode, print_wp_mode. Function pointers allow flexibility to assign chip specific routines for exotic cases. - Prettyprinting of different status register bits is unified. Newer bits can be defined in enum status_register_bit and description written in statreg_bit_desc[][]. Functionality exposed through struct status_register member. Patch from https://mail.coreboot.org/pipermail/flashrom/2016-July/014718.html Change-Id: Id9ce4d5f8f3730d07f4959a80822e55f5287c3ff Signed-off-by: Hatim Kanchwala <hatim at hatimak.me> Signed-off-by: Giuseppe Lippolis <giu.lippolis@gmail.com>
- struct flashchip contains pointer to a struct wp (for allowing flexibility of reuse), which in turn has members to represent protection ranges and, pointers to functions to fetch bp_bitmask, set protection range, disable any protection, and print protection range table. Function pointers allow flexibility to assign chip specific routines for exotic cases. - Print table of valid ranges for write protection - Automatically fetches bit names from status_register->layout to make list more meaningful - Disabling of block protection is unified (we can decommission the various spi_disable_blockprotect() functions from spi25_statusreg.c) - Write protection mode(s) of status register(s) are automatically queried and disabled (courtesy of struct status_register) - BP bitmasks are fetched from wp->bitmask - For around 50% of chips supported by flashrom (as of writing this), ranges are automatically generated based. This is especially true of GigaDevice and Winbond chips. For many other chips the generated range can be used as boilerplate to start with. - The presence of a CMP bit is automatically handled for printing as well as setting range (as long as a standard is followed - please refer comment under compute_cmp_ranges label in sec_block_range_pattern() function in writeprotect.c) Change-Id: Ib8827e84bda98ac509fb3ac19914f4800e752c39 Signed-off-by: Hatim Kanchwala <hatim at hatimak.me> Signed-off-by: Giuseppe Lippolis <giu.lippolis@gmail.com>
- struct status_register defines added for the following chips (66 in total) - - AMIC(4) : A25L080, A25LQ16, A25LQ32A, A25L032 - Macronix(15) : MX25L6408E, MX25L6406E, MX25L1605D, MX25L3205D, MX25L6405D, MX25L1608D, MX25L3208D, MX25L6408D, MX25L6436E, MX25L6445E, MX25L6465E, MX25L12865E, MX25L12845E, MX25L12835F, MX25L1673E - GigaDevice(41) : GD25LQ16, GD25LQ40, GD25LQ80B, GD25LQ40B, GD25LQ64C, GD25LQ80, GD25LQ128C, GD25LQ32C, GD25LQ16, GD25LQ40, GD25LQ80B, GD25LQ40B, GD25LQ64C, GD25LQ80, GD25LQ128C, GD25LQ32C, GD25Q16B, GD25Q32B, GD25Q64B, GD25Q10, GD25Q16, GD25Q20, GD25Q40, GD25Q80, GD25VQ16C, GD25VQ80C, GD25Q16C, GD25Q40C, GD25VQ21B, GD25VQ41B, GD25Q21B, GD25Q41B, GD25Q80B, GD25Q128, GD25LQ05B, GD25LQ10B, GD25LQ20B, GD25Q32C, GD25Q64C, GD25Q127C, GD25Q128C - Winbond(6) : W25Q80, W25Q16, W25Q32, W25Q40BL, W25Q64FV, W25Q128FW - 16 of the above support new infrastructure (in flashchips.c) (WIP) - 19 unique struct definitions were required to represent all of the above chips. - Note that quite a few chips don't have support in flashrom (yet). Change-Id: I1759ab3927ec6d4efd85b219ca4659d60e71c28e Signed-off-by: Hatim Kanchwala <hatim at hatimak.me> Signed-off-by: Giuseppe Lippolis <giu.lippolis@gmail.com>
- struct wp defines added for the following chips (21 in total) - - AMIC(4) : A25LQ032, A25LQ32A, A25L080, A25LQ16 - Macronix(12) : MX25L1605D, MX25L1608D, MX25L1673E, MX25L6406E, MX25L6408E, MX25L6405D, MX25L3205D, MX25L3208D, MX25L6436E, MX25L6445E, MX25L6465E, MX25L6473E - GigaDevice(5) : GD25LQ40, GD25LQ80, GD25LQ16, GD25Q16, GD25Q16B - All of the above support new infrastructure (in flashchips.c) (WIP) - 6 unique struct definitions were required to represent all of the above chips Change-Id: I6390d6e16edd56ae797aa71b0b85e3e97ee0d239 Signed-off-by: Hatim Kanchwala <hatim at hatimak.me> Signed-off-by: Giuseppe Lippolis <giu.lippolis@gmail.com>
- New infrastructure is used to read status register (for chips that have support for struct status_register) throughout spi25.c. - New infrastructure is used to prettyprint status register and write protection mode of status register (for chips that have support for struct status_register) in flashrom.c. - New disable from access protection infrastructure is used (for chips that have support for struct wp) in flashrom.c Change-Id: I34c74f20cf4978f47f344ce993bd31ba0303242e Signed-off-by: Hatim Kanchwala <hatim@hatimak.me> Signed-off-by: Giuseppe Lippolis <giu.lippolis@gmail.com>
- Following new CLI options added - - print-status-reg : print detailed contents of status register(s) - print-wp-status : print write protection mode of status register(s) - wp-list : print list of write protection ranges - wp-enable : enable write protection of status register(s) to optionally supplied MODE argument - wp-disable : disable any write protection of status register(s) - wp-set-range : set write protection range to supplied range - Updated man page with new CLI options Change-Id: I48bd685fd855712559826ce071d82b222da05bca Signed-off-by: Hatim Kanchwala <hatim@hatimak.me> Signed-off-by: Giuseppe Lippolis <giu.lippolis@gmail.com>
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This pull req apply the patch from the flashrom mailing list sent by Hatim Kanchwala.
Here the post:
[flashrom] [PATCH 0/4] Initial OTP/Security Register infrastructure