gap: .t27 has no clocked/sequential construct — spec-first datapath is combinational-only (blocks Phase 2)

[gHashTag]

The spec-first .t27 compute path lowers to combinational Verilog only. This blocks a real streaming accelerator (Phase 2 of the BitNet roadmap): weights-from-BRAM, activation streaming, per-cycle accumulation all need clocked state.

Evidence

• gen-verilog specs/fpga/uart.t27 emits 0 always @(posedge clk) blocks.
• A module-level var count : u8 becomes a reg, but its update lives inside a combinational function (count = count + 1; in fn tick), never in a clocked process — so the state is never actually registered/advanced by a clock.
• debug-hir on any spec shows always_blocks: [] and ternary_cores: []. The HIR emitter has emit_always_block (compiler.rs:17968) and emit_ternary_core, and clocked always-blocks are constructed in unit tests (compiler.rs:19729), but the AST→HIR lowering never populates them from source.

Two paths forward for Phase 2

1. Compiler feature: add a clocked-process / sequential-block construct to the .t27 grammar (e.g. on posedge(clk) { ... } or a registered-var semantics) and wire the AST→HIR lowering to populate always_blocks (the emitter already exists). Then a streaming ternary accumulator can be spec-first.
2. Hand-written engine: the clocked datapath already exists in the hand-written SV emitters (pipeline_stage2_compute, etc.), and the spec-first dot27 is bit-exact equal to the hand-written trit27_dot_product (feat(ternary): spec-first ternary MAC dot product (.t27), bit-exact vs handwritten #1743). So Phase 2 could instead complete the hand-written bitnet_engine_top (fix input≡weight aliasing + write-back + quantizer wiring; test: bitnet_top asserts stale contract (busy + mem tie-off) vs current gen-bitnet-engine-top #1726) using the proven-equivalent compute.

This is the crux of the on-hardware MVP path; recording it so the choice is deliberate.

[gHashTag]

Decomposed implementation plan (path 1 — add a clocked construct to the spec-first compiler). Investigation confirms the shape:

• HirModule::convert(ast) (compiler.rs:17350) lowers each fn via convert_fn_to_comb — always combinational, never populates always_blocks.
• The HIR emitter already handles clocked logic: emit_always_block (compiler.rs:17968) renders always @(posedge clk) begin if(!rst_n)… else … end from a HirAlwaysBlock { edge, clock_name, reset_name, body: Vec<HirAlwaysStmt> }.
• Caveat: all current specs use the direct gen-verilog path (gen_verilog), NOT gen-verilog-hir. So clocked support must land in whichever path the accelerator specs will use.

Steps

1. Grammar/parser — add a sequential block, e.g. on posedge(clk) reset(rst_n) { <stmts> } (or a reg-qualified module var with a designated step() fn). Parse into a new AST node (NodeKind::SeqBlock) carrying edge + clock + reset + body.
2. HIR lowering — in HirModule::convert, map SeqBlock → HirAlwaysBlock; lower each body statement to HirAlwaysStmt (assignments become non-blocking inside a clocked block; if/else, for already have HirAlwaysStmtKind variants). Reuse the existing emit_always_block.
3. Direct gen-verilog path — mirror a minimal clocked emitter there (or route stateful specs through the HIR path), since the BitNet specs use gen-verilog.
4. Semantics — module-level var inside a seq block is a registered reg; reset clears it; en gates updates. One clocked accumulator (acc <= first ? dot : acc + dot) is the MVP.
5. Verify — a .t27 streaming accumulator that feeds one chunk/cycle must gen-verilog to always @(posedge clk), iverilog-simulate, and match a golden multi-cycle accumulation. Reseal all affected specs; trust CI validate.

Scope/risk

Multi-part (parser + HIR + emitter + reseal). Bigger than a single autonomous increment — best done as a focused, reviewed change. Once clocked var state exists, the spec-first dot27 (bit-exact vs the hand-written trit27_dot_product, #1743) can be wrapped in a streaming pipeline stage = spec-first Phase 2.

[gHashTag]

Additional Phase-2 blocker found: the direct gen-verilog module interface is fixed (clk, rst_n, en, ready) with no data ports, so even a clocked accumulator couldn't stream chunks in/out. So Phase 2 is really the HIR path (which already models ports/memories/fifos in its emitter) wired up from source — not a small slice of the direct path. Confirms step 3 of the plan (route stateful/streaming specs through HIR) is the load-bearing one.