feat(fpga): FPGA pipeline restoration — XDC fix, t27c fpga-build, synthesis test

[gHashTag]

Summary

Restore and harden the FPGA synthesis pipeline from .t27 specs through Verilog generation to bitstream, following L7 NO-NEW-SHELL (no new .sh on critical path).

Background

FPGA specs exist in specs/fpga/ (mac, uart, spi, bridge, top_level + testbenches), with constraints for QMTECH XC7A100T and Arty A7 boards. The t27c gen-verilog path works (70 Verilog modules generated, all pass suite). Legacy scripts/fpga/build.sh and flash.sh are pre-L7 grandfathered but should not be extended.

Tasks

• XDC pin conflict fix — qmtech_a100t.xdc had 13 duplicate pin assignments (V17/U17 triple-conflict between UART TX, LED, MAC result). Fixed: UART changed from 8-bit parallel to 1-bit serial; all pins unique.
• t27c fpga-build subcommand — Replace build.sh with a Rust-native t27c fpga-build command that generates Verilog + top-level wrapper + runs Yosys/NextPNR via Docker or local tools. Honors L7 NO-NEW-SHELL.
• Top-level wrapper update — zerodsp_top.v ports aligned with fixed XDC: 1-bit UART, SPI master, 8 LEDs, 32-bit MAC result.
• Synthesis smoke test — Verify t27c fpga-build --smoke (gen-only) and full synthesis via hdlc/oss-cad-suite Docker image.
• Seal refresh — Re-seal FPGA specs after XDC/top-level changes.

Acceptance Criteria

1. t27c fpga-build --smoke generates synthesizable Verilog with no pin conflicts
2. t27c suite passes with 0 failures on FPGA-related specs
3. No new .sh files created (L7 compliance)
4. XDC has 0 duplicate pin assignments

Affected Files

• specs/fpga/constraints/qmtech_a100t.xdc (fixed)
• bootstrap/src/main.rs (new fpga-build subcommand)
• scripts/fpga/Makefile (updated top-level wrapper)

Laws

• L1 TRACEABILITY: This issue gates all FPGA PRs
• L2 GENERATION: Verilog is generated, not hand-edited
• L4 TESTABILITY: Specs already have test/invariant/bench blocks
• L7 UNITY: No new shell scripts; use t27c + Makefile

Closes #(this issue)