feat(fpga): FPGA pipeline restoration — XDC fix, t27c fpga-build, seal collision resolution#344
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feat(fpga): FPGA pipeline restoration — XDC fix, t27c fpga-build, seal collision resolution#344
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…P endpoints - Optimizer: CSE, dead store elimination, unary constant folding - Typechecker: unused variable detection warnings - Rust codegen: ExprSwitch (match) support - New CLI commands: size, analyze, diff, ci, watch, inspect, outline, callgraph, health, deadcode, metrics, flatten, deps-tree, todo - New HTTP endpoints: /size, /inspect, /deadcode, /metrics - New compiler specs: lexer, linker, optimizer, pipeline, stdlib, typechecker, diagnostics, meta_compile - New test framework specs: core, runner, graph_drift_detection, property_test_template, verilog_bench_harness - Regenerated all 94 seal files (4 backends: Zig, Verilog, C, Rust) - Suite: ALL TESTS PASSED (9 phases, 0 failures) - Both builds (--release, --release --features server) clean with 0 warnings
…oll, improved fmt - Optimizer: loop unrolling for small for-loops (<=4 iterations) - Typechecker: tail call detection, struct field validation - Improved t27c fmt: full roundtrip (params, return types, all stmts) - New commands: rename, spellcheck (Levenshtein), coverage, validate - deadcode --repo: batch deadcode analysis for entire repo - 51 total CLI commands, 7015 compiler LOC - Suite: ALL TESTS PASSED, 0 warnings in both builds
…stack, dupes, init, exports, api-diff - New CLI commands: xref, bench-compile, minify, count, check-deps, stack, dupes, init, exports, api-diff (61 total commands) - Typechecker: const reassignment detection, param count warning, enum variant exhaustiveness check - Rust codegen fix: and->&&, or->|| - HTTP /coverage endpoint - Regenerated all 94 seals - Suite: ALL TESTS PASSED, 0 warnings in both builds - 7093 compiler LOC
…on commands; unreachable code detection in typechecker
…commands; recursive struct detection in typechecker
- Add t27c fpga-build --smoke subcommand for Verilog generation from specs/fpga/*.t27 - Fix qmtech_a100t.xdc: UART from 8-bit parallel to 1-bit serial, eliminate 13 duplicate pin assignments - Rename colliding modules: TernaryMemory->ISAMemoryOps, bigint->TernaryBigInt, PropertyTestTemplate->PBTTemplate - Reseat all 129 specs: suite now passes with 0 failures Closes #336
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Implement two CI-required subcommands: - validate-seals --pr-files: verify seals match for PR-scoped spec files - validate-phi-identity: validate L5 invariant phi^2 + phi^-2 = 3 Also fix CI workflow to use workspace target path.
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Summary
t27c fpga-build --smokesubcommand: Generates 5 Verilog modules (mac, uart, spi, bridge, top_level) + top-level wrapper fromspecs/fpga/*.t27specsqmtech_a100t.xdchad 13 duplicate pin assignments (UART was 8-bit parallel). Fixed to 1-bit serial UART, SPI on Pmod, unique LED pins, 32-bit MAC debug interfacespecs/isa/ternary_memory.t27:TernaryMemory→ISAMemoryOpsspecs/ternary/bigint.t27:bigint→TernaryBigIntspecs/test_framework/property_test_template.t27:PropertyTestTemplate→PBTTemplateTest plan
t27c fpga-build --smoke— passes, generates 5 modules + wrappert27c suite— 0 parse failures, 0 gen failures, 0 seal mismatchesmake synthinscripts/fpga/withhdlc/oss-cad-suiteimageCloses #336
φ² + 1/φ² = 3 | TRINITY