feat(fpga): instantiate UART/SPI/TopLevel modules in synthesis, fix type-suffixed literals

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Problem

1. Lexer bug: Type-suffixed literals like 3u32 were split into two tokens (3 + u32), corrupting the AST and producing invalid Verilog expressions like (u32 << bit_pos).

2. FPGA synthesis: Top-level wrapper was a bare heartbeat counter — no spec-generated modules were instantiated. Yosys synthesis only read the wrapper file, not the sub-modules.

Solution

1. Lexer fix: After parsing a number literal, consume known type suffixes (u8, u16, u32, u64, usize, i8..i64, f16, f32, f64).

2. Wrapper update: Top-level zerodsp_top now instantiates ZeroDSP_UART, SPI_Master, and ZeroDSP_TopLevel with LED[1..3] showing ready status.

3. Yosys script fix: Reads all working Verilog modules (uart, spi, top_level, wrapper) instead of only the wrapper.

Verification

• Yosys synthesis PASSES: 112 cells, 27 FDRE, 3 submodules instantiated
• t27c fpga-build --smoke passes (5 modules + wrapper generated)
• t27c fpga-build --docker false passes (full synthesis)
• t27c validate-phi-identity passes (L5)

Remaining (deferred)

• mac.v and bridge.v have deeper codegen issues (assignment targets, reference operators) — tracked separately
• Bitstream generation requires Vivado (not Yosys/nextpnr for Artix-7)

Closes #141