fix(compiler): const_propagate LHS guard, reassigned var check, &&/|| lexer#365
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fix(compiler): const_propagate LHS guard, reassigned var check, &&/|| lexer#365
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Three fixes: 1. const_propagate: skip LHS of StmtAssign (was replacing assignment targets with literal 0, producing '0 = ...' in Verilog) 2. const_propagate: don't propagate vars that are reassigned later (was replacing 'result' with '0' in RHS even after mutation) 3. Lexer: recognize && and || as multi-char tokens, parse as logical and/or operators instead of bitwise &/| MAC and Bridge specs now parse in Yosys frontend (remaining issues: array+field access 'a[i]_field' and expression grouping precedence). Closes #359
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Summary
Three critical compiler fixes for Verilog codegen correctness:
const_propagate LHS guard —
replace_ident_with_literalandpropagate_identnow skipchildren[0]ofStmtAssignnodes, preventing assignment targets from being replaced with literals (was producing0 = (0 | ...))Reassigned variable check —
const_propagatenow checks if a variable is reassigned before propagating its initial value. Previouslyconst result = 0; result = result | ...would replace allresultwith0&& / || lexer tokens — Lexer now recognizes
&&and||as multi-char tokens. Parser maps them to logical and/or operators. Previously&&was two&(bitwise AND) tokensImpact
result = (result | pack_trit(...))now correct (was0 = (0 | ...))&&expressions now produce&&in Verilog (was& &)a[i]_field) and expression grouping need further workCloses #359