fix(codegen): iverilog-clean gen-verilog + BPSK modem spec#1250
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Port of the gen-verilog/parser fixes to master so datapath specs compile & simulate: (1) parse_const_decl consumes trailing ';' -> consecutive const/var runs no longer dropped (uart 1->8 localparams, 31->0 iverilog errors); (2) integer literals render as decimal (0x/0b/_ -> valid Verilog); (3) guarded early return rewritten to if/else; (4) struct-field regs named by the holding var; (5) zero-arg functions get a dummy input; (6) function bodies use named begin blocks. Existing ExprCast handling kept. New specs/fpga/bpsk.t27 (ZeroDSP_BPSK, trios-mesh BPSK modem core) iverilog- compiles AND simulates: 13 embedded test assertions pass; correlate(Barker)=13, inversion=-13, sidelobes -5/+5, sync gate, frame=21. uart/mac clean too. Closes #1245 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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#1255) Reseal every spec so suite seal-verify is green after the gen-verilog change (#1250) shifted gen-hashes for most specs; also clears pre-existing spec-hash drift + missing seals. Three spec pairs shared a module name and collided on their <dir>_<Module>.json seal (FeedForward, String, malformed "[]const u8") -> rename the second of each pair (FeedForwardNetwork / SacredGovernance / FacultyBoard). Suite: parse/typecheck/gen(x4)/seal-verify 514/514. Closes #1254 Co-authored-by: gHashTag <deborahnelson8788726@gmail.com> Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
This was referenced Jul 2, 2026
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Closes #1245. Makes
t27c gen-verilogemit iverilog-compilable, simulatable RTL for datapath specs, and adds the trios-mesh BPSK modem core asspecs/fpga/bpsk.t27.Backend fixes (
bootstrap/src/compiler.rs)parse_const_declnow consumes the trailing;(a stray;made the module-body loop skip subsequent decls). uart: 1 -> 8 localparams, 31 -> 0 iverilog errors.0x/0b/_integer literals render as decimal (valid Verilog).if/elseso the return is not clobbered (last-write-wins).varname (matches field access).input(Verilog forbids port-less functions).Existing
ExprCastcast handling kept as-is (master's validated version).New
specs/fpga/bpsk.t27(ZeroDSP_BPSK)BPSK serializer + Barker-13 preamble + integer correlator + threshold sync. iverilog-compiles AND simulates: 13 embedded test assertions pass; hierarchical checks give correlate(Barker)=13, inversion=-13, sidelobes -5/+5, sync gate, frame=21. uart/mac now iverilog-clean too (fpga clean 1 -> 3 of 34).
Validation
suite: parse / typecheck / gen(Zig/Rust/Verilog/C) 514/514.phi^2 + phi^-2 = 3 | TRINITY