feat(fpga): W401 cold-POR protocol hardening and board-less CI guards (#1303)#1304
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…old-POR CCLK sweep, default bitstream verified, board-less CI guards Wave Loops 397-401 close the FPGA SPI boot root cause and harden the protocol: - W397: boot-log, STAT decoding, cold-POR decision tree. - W398: patch-cor0 / cclk-variants, bit-config assertions. - W399: automated cclk-sweep, sweep-report, measure-cclk helper. - W400: default ternary_mac_demo_top_200t.bit verified to boot from flash across OSCFSEL 0..5; CCLK timing hypothesis closed. - W401: smoke-gate canonical assertions (IDCODE, SPI x1, CCLK startup, OSCFSEL=0, no CRC writes), boot-protocol checklist, multi-format CCLK CSV parser with unit tests, dry-run sweep CI guard, close-out reports. Verification: ./scripts/tri test 575/575 PASS. Closes #1303
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Wave Loop 401 closes #1303 by hardening the cold-POR SPI-boot protocol and adding board-less guards around the W400 physical result.
Summary
tri fpga smoke-gatenow asserts the canonical bitstream config: IDCODE0x03636093, SPI x1, CCLK startup,OSCFSEL=0, and no CRC writes.tri fpga boot-protocol(interactive and--checklistmodes) so the cold-POR steps are explicit and printable.tri fpga measure-cclk --csvnow auto-detects DSView / PulseView / Saleae CSV exports and reports frequency / duty cycle; unit tests added.cclk-sweep/sweep-reportpipeline and asserts sixOSCFSELrows.fpga/HARDWARE_SSOT.md, close-out reports, and cooperation variants for W402.Verification
Deferred
AC5 (physical CCLK measurement on pin P12) requires an oscilloscope/logic-analyser capture and is deferred to W402.
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