promote bcd → strict bitexact (2-digit packed instance, 3 witnesses) - #1319
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PR DashboardGenerated at: 2026-07-04 12:06:21 UTC
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July 4, 2026 12:08
…tance)
BCD was structural (generic variable-width, u4_per_digit, no single layout).
This pack fixes the concrete 2-digit packed instance (8-bit: tens[7:4]*10 +
ones[3:0], range 0..99) - the same instance decoded on AX7203 silicon
(corona-decode-bcd, HW Tier-E 100/100) and iverilog-witnessed on bcd_decode.v.
Vectors: 100 valid codes 00..99 (exhaustive over the valid range), abs_error=0.
Three independent witnesses recorded:
1. Python golden (tens*10+ones, integer exact) - 100/100 abs_error=0
2. iverilog 13.0 sim of bcd_decode.v - 256/256 bit-exact (incl. invalid-nibble
mod-128 + valid flag), independent of the Python oracle
3. FPGA HW (corona-decode-bcd, AX7203 IDCODE 0x13636093) - 100/100 @160000
INDEX: bitexact_packs 69 -> 70, structural_packs 14 -> 13.
Generic-BCD variable-width nature noted in catalog.instance + format_notes;
invalid nibbles (0xA..0xF) excluded from the round-trip claim (documented policy).
Per recipe-sw-bitexact gate (independent decoder + exact oracle + 2nd witness).
Status tag: [verified SW] (iverilog) + [izmereno na kremnii] (HW Tier-E).
Catalog = 83 unchanged.
Closes #1321
- Replace em-dash (U+2014) with ASCII hyphen in bcd_conformance_v0.json (fixes integrity-gate Check D parse error: ascii codec byte 0xe2). - Refresh bcd sha256 in INDEX_all_formats.json to match file byte-for-byte (fixes integrity-gate Check C sha_drift). - Add docs/NOW.md entry for the bcd promotion (fixes check-now-freshness). No vector values changed; 100/100 abs_error=0 unchanged. Catalog = 83. Closes #1321
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What
Promote
bcdfromstructural→ strictbitexact(+1 SW axis: bitexact 69 → 70, structural 14 → 13).Why bcd was structural: generic BCD is variable-width (
u4_per_digit, no single fixed layout) — a bit-precise round-trip isn't well-defined for the generic class. This pack fixes the concrete 2-digit packed instance (8-bit:tens[7:4]*10 + ones[3:0], range 0..99) — the same instance decoded on AX7203 silicon and iverilog-witnessed.Gate (recipe-sw-bitexact: independent decoder + exact oracle + 2nd witness)
Vectors: 100 valid codes 00..99 (exhaustive over the valid range),
abs_error=0. Three independent witnesses:tens*10+ones, integer exact)bcd_decode.v(trinity-fpga)0x13636093)Witness #2 is the meaningful SW-bitexact witness: real Verilog fixed-width sim, not a Python transcription. Invalid nibbles (0xA..0xF) excluded from the round-trip claim; their RTL behaviour documented in
format_notes.INDEX delta
Honesty
catalog.instance/format_notes.Closes #1321