feat(fpga): instantiate UART/SPI/TopLevel modules in synthesis, fix type-suffixed literals

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Summary

• Lexer fix: Type-suffixed literals (3u32, 1usize, etc.) now correctly parsed as single Number token — prevents AST corruption and invalid Verilog codegen
• FPGA synthesis with real modules: Top-level wrapper instantiates ZeroDSP_UART, SPI_Master, ZeroDSP_TopLevel with LED ready-status indicators
• Yosys script fix: Reads all working Verilog modules (uart, spi, top_level, wrapper) for full hierarchy synthesis

Verification

Test	Result
t27c fpga-build --smoke	PASS (5 modules + wrapper)
t27c fpga-build --docker false	PASS (Yosys synthesis: 112 cells, 27 FDRE, 3 submodules)
t27c validate-phi-identity	PASS (L5)
UART/SPI/TopLevel Verilog	Yosys parse OK
MAC/Bridge Verilog	Deferred (deeper codegen issues)

Closes #359