fix(compiler): const→reg in Verilog codegen, 5 FPGA specs parse in Yosys#363
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fix(compiler): const→reg in Verilog codegen, 5 FPGA specs parse in Yosys#363
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Previously, const declarations in function bodies were emitted as commented-out '// const ...' in Verilog, making variables invisible to the synthesizer and causing cascading errors (assignments to 0). Now both const and var declarations emit 'reg' in Verilog, which is correct for function-local variables in synthesizable RTL. Also: all 5 FPGA specs pass Yosys Verilog frontend parsing. Synthesis passes with 3 instantiated modules (UART, SPI, TopLevel). MAC and Bridge have remaining parser-level issues (tracked separately). Closes #359
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Apr 14, 2026
Closes #363 Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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Summary
constdeclarations now emitregin Verilog instead of commented-out// const. This makes variables visible to Yosys and fixes cascading parse errors.Verification
0 = ...issue)& &issue)Full synthesis with UART + SPI + TopLevel: 112 cells, 27 FDRE, 3 submodules.
Closes #359