Sparse-V: RISC-V Integrated Structured Sparsity Accelerator

Overview

Sparse-V is a highly efficient hardware accelerator designed for TinyML applications on edge devices. It leverages 2:4 Structured Sparsity to skip redundant computations (zero-valued weights), delivering high-performance matrix multiplication with minimal silicon area usage. The IP is wrapped with an AXI4-Lite interface, making it plug-and-play compatible with RISC-V processors (e.g., Ibex, CV32E40P).

Key Performance Metrics

Metric	Baseline (RISC-V CPU)	Sparse-V (This Work)	Improvement
Latency (4x4 Matrix)	~128 Cycles	9 Cycles	14.2x Speedup 🚀
Throughput	Sequential	Parallel (4 PE)	4x Throughput
Area Cost	N/A	37 LUTs / 68 FFs	<1% FPGA Area
Efficiency	Standard	50% Weight Compression	2x Memory Bandwidth

🛠️ Tech Stack

• Hardware Design: SystemVerilog (IEEE 1800-2017)
• Interface: AXI4-Lite Slave Protocol
• Verification: Vivado 2025.1 Simulator & Python (NumPy/TensorFlow)
• Synthesis: Xilinx Vivado (Target: Artix-7 / Zynq-7000)

Architecture

The design consists of a Systolic Array-like structure where 4 Processing Elements (PEs) operate in parallel. Each PE handles a specific row of the weight matrix, utilizing indirect indexing to fetch activations based on sparsity metadata.

Verification Results (Real-World AI Workload)

The hardware core was tested against a Scikit-Learn MNIST Digit Recognition model. The simulation verified Bit-Exact Accuracy with the software model using 2:4 Structured Sparsity and INT8 Quantization.

Feature	Specification	Status
Workload	MNIST Digit Classification Layer	✅ Verified
Input Data	Real Handwritten Digit Pixel Vectors	✅ Verified
Arithmetic	Signed INT8 (Two's Complement)	✅ Verified
Accuracy	100% Match with Python Reference	✅ Verified

Simulation Output Log

-> Writing Input Vectors (Real MNIST Data)...
-> Starting Core...
-> Reading Results...
Read Address: 0x14, Data:   1384 (Match)
Read Address: 0x18, Data:  -4224 (Match)
Read Address: 0x1c, Data:  -4682 (Match)
Read Address: 0x20, Data: -10058 (Match)
Hardware Latency: ~14 Cycles


##  Repository Structure

```text
Sparse-V-Accelerator/
├── src/                    # SystemVerilog Design Files
│   ├── sparse_core.sv      # The math engine (4 Parallel PEs)
│   ├── sparse_pe.sv        # Processing Element logic
│   ├── sparse_pkg.sv       # SystemVerilog data types & structs
│   └── axi_sparse_wrapper.sv # AXI4-Lite Bus Interface
├── sim/                    # Simulation & Testbenches
│   ├── tb_axi_sparse_wrapper.sv # Master Testbench (CPU Emulation)
│   ├── weights_nz.mem      # Compressed Weights (Generated by Python)
│   └── indices.mem         # Sparsity Indices (Generated by Python)
├── scripts/                # Utility Scripts
│   └── train_mnist_sparse.py # Python script for pruning & packing
└── README.md               # Project Documentation