v0.5.0 — the structural-advantage release

Six capabilities the incumbents structurally cannot ship — binary files,
ordinal identity, and GUI-first architectures forbid every one of them.

The type system for hardware (ADR-0015)

Pins carry electrical envelopes; net voltages derive from rail names
(+3V3 -> 3.3 — a name that parses is a contract). 5V into a 3.6V-max pin
is a design-time type error. Rail overload checked against source
capacity, utilization reported even when green, coverage counted so
green never masquerades as verified. schematic_envelope.

Pull requests that show their physics

gitcad-review --base main: per changed design doc — semantic diff,
check delta (violations INTRODUCED vs FIXED vs PRE-EXISTING across ERC /
envelopes / board validation / DRC), before/after renders side-by-side.
The merge gate fails only on introduced violations. Exit 1 = CI gate.

Simulation as tests

to_spice exports the schematic (rails become sources by the same name
contract; unmodeled parts REPORTED, never dropped). sim_check runs
ngspice asserting node voltages — "OUT sits at 2.5 +/- 0.05 V" is now a
check like any other.

Semantic 3-way merge (ADR-0016)

gitcad-merge is a git merge driver keyed by stable identity: features
by id, schematic connectivity by pin. Parallel edits to different
features merge into a document that rebuilds; a net rename merges; the
same pin on two nets conflicts — structured conflicts, never text
markers. The file-lock era ends here.

Requirements as code

gitcad-verify requirements.json: named requirements bound to machine
checks (mass, volume, bbox, ERC, envelopes, rail utilization, DRC) —
the traceability matrix that executes, measured-vs-limit per row.
Unchecked requirements are visible debt, never silent green.

Fab-lot traceability

gitcad-lot record: a physical build pinned to the exact commit and the
sha256 of every artifact sent to the fab; tampering names the file.
Field failure on lot 7? git bisect run gitcad-verify requirements.json.

Plus: the design-review GUI

Tabs 3d | schematics | measure; click-to-select with part info; exploded
-view slider (display-only, #x=0.6 deep links); the electrical sheets
that make up an assembly rendered under its 3D model; point-to-point
measure with vertex snap.

294 tests. Every commit CI-verified green.

v0.4.0 — the schematic-loop release

The schematic human-feedback loop, closed in both directions, plus the
SolidWorks-manual mechanical feature map completed.

ECAD: schematics like KiCad

• .kicad_sch importer — netlists derived geometrically (wire-pin
  connectivity, junctions, labels, power symbols, stacked pins, no-connect
  markers as design intent). Validated pin-group-identical against
  KiCad 10's own netlist exporter on a real 4-board instrument design.
• Sheet-fidelity rendering — imported sheets render exactly as drawn:
  symbol body graphics, real wire routes, junction dots, power flags, in
  KiCad's visual language. The diagram stays a projection; canonical text
  is untouched.
• Sheet authoring (SheetEditor, MCP schematic_author) — agents draw
  schematics: built-in KiCad-convention symbols, wires with waypoints,
  labels/power flags. The netlist is derived from the drawing through the
  same engine that imports KiCad sheets.
• One connectivity engine (ecad/netderive.py) + sheet_parity —
  an edited drawing must still mean the declared netlist, checked.
• Multi-board system ERC (merge_schematics, MCP
  schematic_system_erc) — nets union by name across connectors; on the
  real design it found the genuine issues (analog ground never tied,
  undriven inputs, not-yet-drawn peripherals) with zero noise.
• Copper zones first-class (Gerber G36/G37, DRC polygon clearance,
  connectivity, KiCad import).

MECH: the SolidWorks-intro feature map, done

• loft, sweep, mirror (with fuse), countersink holes — all golden-tested
  against analytic volume oracles
• sketch planes + sketch-on-face (extrude plane= + mode=add|cut)
• section views with exact plane-intersection outlines and 45° hatching
• assembly drawings: balloons numbered by the same assembly_bom that
  feeds procurement, BOM table on-sheet
• exploded views as canonical-text projections with mate-graph
  auto_explode (ADR-0014)
• 2D sketch constraint solver (sketch_solve, ADR-0013) — authoring
  time only, DOF accounting, branch pinned by the drawn guess
• mass properties (model_mass): volume, mass at density, COM, inertia
• FreeCAD .brp import fix (real-world FCStd files)

224 tests. Every commit in this release CI-verified green.

v0.3.0 — the dogfood release

Everything since v0.2.0 — culminating in gitcad building its first real product and fixing every friction point found doing it, same day.

The dogfood (attached: out-altair.zip)

A 4-gas-detector POC (enclosure + battery cradle + ESP32-S3/ADS1220 board + schematic) built entirely through gitcad's MCP tools: rounded-shell housing with window/buttons/LEDs, 2×18650 cradle, fully-routed 2-layer board — ERC/parity/DRC/connectivity/fab all green, exact boolean interference clean, all-checks release with 19 pinned artifacts. The check chain caught 5 real routing errors during the build. The 9-item friction log became the ergonomics release below.

Ergonomics (the friction, fixed)

• route() + pad_position — wrong-net pads refused, SMD sides enforced, auto-vias on layer changes. The Altair routing went from 25 hand-computed tracks (5 caught errors) to six calls passing every check first try
• board_to_model bridge · boss feature · entity select DSL ("plane,zmax") · cylinder(axis=) · degenerate-track gate · missing-inputs guard

Modeling

Sketch profiles (lines+arcs) → extrude/revolve · chamfer · shell · patterns · counterbore holes · DXF R12 export — all volume-oracle tested

Checks & release

DRC engine (net-scoped rule packs) · copper connectivity (unrouted islands + label-blind shorts) · exact interference (measured overlap) · schematic capture + ERC + board parity · release(): every check or no artifacts, sha256 manifest · semantic diff

Import & interop

STEP (round-trip proven) · FreeCAD .FCStd parametric-tree import with proof · KiCad boards · feature recognition: STEP → parameterized model, residual < 1e-6 or refused · SolidWorks bulk-export path

Platform

Workspace split: gitcad-core / gitcad-mech / gitcad-ecad / gitcad namespace packages (ecad installs skip the 400MB kernel; core self-containment is now an invariant) · registry live (github.com/gitcad-xyz/registry, interface-semver enforced in CI) · web viewer with assemblies · associative dimensions · 24 MCP tools

157 tests · CI green · https://gitcad.xyz

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v0.2.0 — the part standard, importers, and the full ECAD check chain

Everything since v0.1.0 — one day of development, every block CI-verified.

The Part standard (ADR-0008–0011)

• Parts are the universal unit; an assembly IS a part (full nesting). Domain-neutral interfaces: envelope + named frames + typed ports (mech.bolt, elec.pin, ...)
• Interface-semver, machine-enforced: a moved mounting hole requires a MAJOR bump — check_release rejects under-bumped releases mechanically
• Lockfiles: ^/~/exact constraints resolved deterministically, pinned by canonical-content hash — builds reproducible from a git tag forever
• Derived interfaces: boards derive part.json from mounting holes + outline; models derive envelopes from built geometry. Change the board, the release gate reacts — nothing hand-maintained

Importers — bring your existing work

• STEP (round-trip verified to 1e-6), FreeCAD .FCStd (reads embedded breps — no FreeCAD needed), KiCad .kicad_pcb (v5–v9)
• Honest ImportReport on every import: what came in, what was approximated, what was dropped. >2 routed copper layers is a refusal, never silent loss
• Imports pinned by sha256 — builds fail loudly on swapped geometry

The full ECAD check chain

• Schematic capture (text-first netlist, typed pins) + ERC (pin-type conflict matrix, undriven inputs, unpowered power pins)
• Schematic↔board parity (the ECO check, both directions)
• DRC engine: net-scoped rules in canonical, shareable rule packs — clearance, track width, annular ring, drill sizes, hole spacing, edge clearance. It caught a real routing bug in our own demo the day it was born.
• The blinky example now runs capture → ERC → layout → parity → DRC → fab-validate → Gerbers in one script

Correctness hardening (independent review, P0–P4 fully closed)

• One canonicalization policy (NaN rejected, −0.0 normalized, int≡float) across every serializer
• Value-based feature ids; duplicate ids rejected at load (the git-merge failure mode)
• Identity wired end-to-end: stable entity ids assigned at build, persistable registry, and fillet-by-entity-id that survives upstream edits — the topological-naming promise, implemented and tested
• Honest verification: null-kernel fallback can't masquerade as geometry checks (geometry_verified on every MCP response); OCP imports confined to the kernel seam by invariant test; structured MCP errors; transmit-safe fingerprints; ADR-0007 scrub + similarity gate completed

Attached artifacts (generated by examples/)

bracket.step / bracket.pdf — model → STEP + dimensioned drawing
blinky-fab.zip — Gerber X2, Excellon (PTH+NPTH), pick-and-place, schematic, manifest

99 tests · CI green on py3.10/3.12 + full OCCT with end-to-end demos · https://gitcad.xyz

🤖 Generated with Claude Code

v0.1.0 — first manufacturing-capable release

gitcad can now take a text model all the way to files you can send to a manufacturer.

Mechanical

• Full OCCT kernel backend: primitives, booleans, fillets, rigid transforms, entity enumeration, geometric validation, mass properties
• STEP (ISO 10303-21) and STL export
• Drawing engine: OCCT hidden-line-removal → third-angle front/top/right/iso views, auto-scaled onto A4/A3/A2 with overall dimensions, title block — SVG + PDF (dependency-free writer)

Electrical

• Text-first 2-layer board model (components/footprints/pads/tracks/vias) with fab-readiness validation
• Gerber X2 writer: top/bottom copper, top/bottom solder mask, silkscreen, board profile
• Excellon drill file, pick-and-place CSV, manifest — one-call fab package export
• Deterministic by construction: the same board text yields byte-identical Gerbers on any machine

Platform

• MCP tool surface (model_new/feature_add/model_validate/model_measure/model_export/model_drawing/board_validate/board_export_fab) — the primary interface; the Python API binds the same handlers
• Stable entity identity (the topological-naming fix), canonical text documents, three-tier test corpus (26 tests), privacy-preserving bug reducer, CI

Attached artifacts (generated by examples/)

• bracket.step / bracket.pdf — demo mounting plate, model → STEP + dimensioned drawing
• blinky-fab.zip — demo LED board, full Gerber/drill/PnP package

pip install -e ".[dev,occt]"
python examples/bracket.py
python examples/blinky.py

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