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[bug] Memory Layout 未勾选Default的分区, 应该也要被统计到 ROM Total 中 #561

Description

@Huyil

#559 相同问题

  1. 配置额外的rom地址与大小, 并且不勾选Default, 因为Default控制的是编译器是否自动使用该内存, 而是否包含内存空间由填入的ROM地址与大小配置
Image
  1. 右键.c 配置rom地址指定到外部rom, 使用MDK可以正常编译, 使用eide显示rom不足
Image Image Image

3.mdk编译后map对应位置

Image Symbol Table
Local Symbols
Symbol Name Value Ov Type Size Object(Section)
.constdata 0x0000b869 Section 64 fdiv.o(.constdata)
fdiv_tab 0x0000b869 Data 64 fdiv.o(.constdata)
.constdata 0x0000c000 Section 8102 pic_level.o(.constdata)
.constdata 0x01000000 Section 67814 pic.o(.constdata)
.constdata 0x010108e6 Section 21280 ascii1408.o(.constdata)

Global Symbols
Symbol Name Value Ov Type Size Object(Section)
gImage_font1210 0x0000c000 Data 3840 pic_level.o(.constdata)
picArc 0x0000cf00 Data 4200 pic_level.o(.constdata)
frameIndices 0x0000df68 Data 62 pic_level.o(.constdata)
gImage_ble 0x01000000 Data 3240 pic.o(.constdata)
gImage_link 0x01000ca8 Data 360 pic.o(.constdata)
gImage_KRPM 0x01000e10 Data 1342 pic.o(.constdata)
gImage_DIR 0x0100134e Data 2904 pic.o(.constdata)
gImage_fonts 0x01001ea6 Data 22400 pic.o(.constdata)
gImage_battery 0x01007626 Data 4800 pic.o(.constdata)
gImage_logoBig 0x010088e6 Data 32768 pic.o(.constdata)
gImage_ascii0814 0x010108e6 Data 21280 ascii1408.o(.constdata

Expected behavior
1.[重点] flash配置效果与MDK一致, 即: 配置ROM大小直接统计可用空间, 不受到default开关的影响,
2.[次要]可以配置文件存入哪个ROM区域或者同步mdk配置

Screenshots

Desktop (please complete the following information):
版本: 1.128.0 (user setup)
提交: fc3def6774c76082adf699d366f31a557ce5573f
日期: 2026-07-07T15:14:24-07:00
Electron: 42.5.0
ElectronBuildId: 14525058
Chromium: 148.0.7778.271
Node.js: 24.17.0
V8: 14.8.178.33-electron.0
OS: Windows_NT x64 10.0.26200

Additional context
some logs, like: <user_home>/.eide/cl.eide.log

; from keil v5
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************

LR_IROM1 0x00000000 0x0000C000  {    ; load region size_region
  ER_IROM1 0x00000000 0x0000C000  {  ; load address = execution address
   *.o (RESET, +First)
   *(InRoot$$Sections)
   .ANY (+RO)
   .ANY (+XO)
  }
  RW_IRAM1 0x20000000 0x00001000  {  ; RW data
   .ANY (+RW +ZI)
  }
}

LR_ROM1 0x01000000 0x00400000  {
  ER_ROM1 0x01000000 0x00400000  {  ; load address = execution address
    pic.o (+RO)
    ascii1408.o (+RO)
  }
}
LR_IROM2 0x0000C000 0x00005000  {
  ER_IROM2 0x0000C000 0x00005000  {  ; load address = execution address
    pic_level.o (+RO)
  }
}

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