verilog-parser

Task definition:

1. Parse a verilog file (one module) and extract its ports (input, output, inout) to a database (array? table? Hash? Whatever…)
2. Generate an excel file with the following data per port: port name, direction, width, description (empty by default)
3. Compare a verilog file (one module) to an existing excel and report which ports changed and what was changed (new port? Port deleted? Description changed? Width? Direction? Etc)