v0.1.0

First numbered release. Metal (macOS/Apple Silicon) is the shipped
distribution target; CUDA and HIP remain source-build until their CI
runners land (ADR 0018).

Added

• X-source debugging: jacquard xsources + netlist-graph xroots
  (#98). A two-command workflow to answer "why does signal S read X under
  cosim --xprop?" as a static query instead of a trace→guess→re-run loop.
  jacquard xsources <netlist> --config c.json -o xsources.json statically
  enumerates every X-source — unreset/reset DFF Q outputs, SRAM read ports,
  and (with --config) undriven primary inputs — as a schema-versioned JSON
  manifest, names resolved through netlistdb (no GPU required).
  netlist-graph xroots <netlist> <signal> --xsources xsources.json then
  reverse-reachability-walks the signal's cone (through DFF data pins,
  skipping clock/reset), intersects with the manifest, and reports the nearest
  X-source frontier classified by kind; --emit-trace writes a
  --trace-signals list for a confirming --xprop run. DFF/SRAM sources
  resolve by driving-cell instance, so jacquard's net-name canonicalisation
  doesn't break the round-trip. Full guide: docs/x-debugging.md. The cosim
  GPIO-index parser (parse_gpio_index) is now shared with the xsources
  driven-set computation so the two stay consistent.

• Multi-corner support (WS2.4, commits 5822343 / 530bb36 /
  59fde04). opensta-to-ir accepts --liberty NAME=PATH to attach
  Liberty files to named PVT corners (bare paths still go to a
  "default" corner). The Tcl driver runs define_corners + per-scene
  read_liberty -corner, emits one record per (key, corner), and the
  Rust builder dedupes them into IR records carrying
  multi-TimingValue vectors. Consumer side: new --timing-corner <NAME> flag on jacquard sim selects the corner index from
  ir.corners() at load time; defaults to corner 0 when unset. Single-
  corner data continues to work unchanged.

• --timing-report <path.json> end-of-run structured timing report
  (commit 58a7a04). Schema-versioned (schema_version = "1.0.0",
  additive-only per ADR 0008's stability contract). Contains per-cycle
  violation list, per-word aggregates, top-10 worst-slack rankings per
  kind, run metadata, and aggregate stats. Sample fixture at
  tests/timing_ir/sample_reports/two_violations.json. Schema and
  consumer guide live in src/timing_report.rs and
  docs/timing-violations.md.

• --timing-summary human-readable text summary on stdout
  (commit 44e70a0). Independent of --timing-report; either or both
  can be set, the report is built once and routed to the requested
  outputs.

• Symbolic violation messages: setup/hold violation lines now name
  the offending DFFs (top/cpu/regs[7][bit 22] [word=42]) instead of
  bare state-word indices (commit 0432d9a). The [word=N] suffix is
  preserved for grep/tooling. New WordSymbolMap in src/flatten.rs
  built once at sim startup.

• OpenSTA detection + version check (WS-RH.1, commit c9c393b).
  When --sdf is requested but OpenSTA is missing, too old, or fails
  to probe, Jacquard now hard-fails with a remediation message instead
  of silently dropping timing data. Newer-than-tested versions warn but
  proceed. Tested against OpenSTA 3.1.0
  (vendored at vendor/opensta/).

• --timing-report violations cap: per-cycle violations array is
  capped at 100k records by default (~8 MB JSON). Override with
  --timing-report-max-violations <N>; 0 disables the cap.
  stats.violations_truncated records overflow. Setup/hold totals
  and worst-slack rankings always reflect every observed event.

• Pillar B Stages 1+2 (commits c403cc8, 6767c3e): ClockArrival
  IR records emitted by opensta-to-ir; per-DFF capture-side clock
  arrival folded into setup/hold checks with DFFConstraint::clock_arrival_ps.
  Closes the main per-flop skew accuracy lever ahead of Phase 2.

• opensta-to-ir golden-IR regression corpus (WS4, commits
  90558bb / 6997096 / 9e25bc2): seed entry aigpdk_dff_chain covers
  all four IR record types; runner + regen helper + CI hookup in place.

• GF180MCU power-pin + wired-filler shortcuts in
  GF180MCULeafPins::direction_of. Phase 6 left two gaps that only
  surfaced on real post-P&R chip-top netlists (gf180mcu-project- template / wafer.space LibreLane flow): (1) Verilog cell models
  declare power as inout VDD, VSS;, but build.rs only parses
  input/output — so the generated pin table lacked VDD/VSS
  entries, panicking on the first .VDD(...) wired in
  antenna/endcap/fillcap/etc.; (2) cor/fill*/dvdd/dvss
  etc. were assumed to instantiate with empty port lists, but real
  netlists wire all four power pins on every filler instance. New
  short-circuit ahead of the pin-table lookup: any pin named
  VDD/VSS/VNW/VPW/VPB/VNB/VPWR/VGND/DVDD/DVSS/
  AVDD/AVSS resolves to Direction::I (constant external
  driver — the enum has no Inout), and any pin on a known filler
  cell falls through to the same. Three new tests in
  gf180mcu::tests cover the power-pin shortcut, the wired-filler
  shortcut, and a realistic chip-top fixture matching the
  gf180mcu-project-template netlist shape. Advances Phase 7 of
  the GF180MCU enablement plan from "synthetic fixtures only" to
  "real wafer.space post-P&R netlists parse end-to-end".

• Config-driven AHB/APB bus transaction tracing for cosim
  (ADR 0013). Declare buses in sim_config.json (bus_traces) and write
  decoded transactions to CSV via --bus-trace-csv. APB3 is supported
  (GPU captures raw beats, the CPU runs the protocol FSM); AHB-Lite /
  AHB5 are planned. Validated by tests/apb_trace/. See
  docs/bus-tracing.md.

• Prebuilt-binary distribution groundwork (ADR 0018): the Metal
  binary now embeds its kernel library so a downloaded binary is
  relocatable, and cargo binstall metadata is in place. GitHub
  Releases + a Homebrew tap (macOS/Metal) follow.

• netlist-graph drivers --data-only (#100): on sequential cells,
  follow the data (D) pin only and skip clock/set/reset/enable pins,
  so tracing a register stays on the data path instead of diving into
  the clock and reset distribution trees.

• Selective X-propagation (--xprop, #95) for both sim and
  cosim (ADR 0016). Uninitialised state — power-up DFFs, undriven
  primary input pads, and uninitialised SRAM — propagates as x through
  the design and into the output VCD instead of silently reading as 0.
  X is seeded only at genuine X-sources: a prior seed-template bug
  cleared the X-mask over DFF-Q feedback reads, so X never originated and
  any sequential design ran two-state. Undriven primary inputs read X in
  cosim; SRAM writes and preloads clear the per-cell X-mask shadow.
  End-to-end CI guards live in tests/xprop_cosim/. See ADR 0016 and
  docs/plans/cosim-xprop.md.

Changed

• ADR 0006 amended 2026-05-02 (commit a4b1c81): subprocess
  invocation of user-installed OpenSTA from the shipped runtime is now
  permitted, provided OpenSTA is not bundled and not linked into the
  Jacquard binary. Phase 3 (native Rust SDF→IR) is no longer release-
  gating. Background: GPL-3 § 5 ("aggregate") and FSF subprocess/IPC
  doctrine.
• process_events API: now takes a ReportingCtx<'_> bundle
  (word_resolver + violation_observer) instead of two separate
  optional callbacks. Default callers pass ReportingCtx::default().
• Hand-rolled SDF parser deleted (WS3 phase 3.4, commit 9b2eb00):
  --sdf now subprocesses opensta-to-ir, which produces timing IR
  consumed by load_timing_from_ir. The IR path (--timing-ir) is the
  canonical input.
• CLI flag rename (pre-release, no compatibility alias): cosim
  --timing-vcd <PATH> → --output-vcd <PATH> (the output VCD —
  functional by default, timed when --timing-ir/SDF is supplied), and
  sim --timing-vcd → --timed. Fixes a misnomer that steered pre-PnR
  functional users away from the one flag they needed.

Fixed

• cosim warns when the positional netlist argument differs from the
  config's netlist_path (the positional wins; logs no longer silently
  describe a different netlist than the one running).
• Progress logging no longer floods single-tick runs — it now fires once
  per ~100k-edge window regardless of batch mode.
• Tracing docs corrected: traced nets land in --output-vcd only (not
  --stimulus-vcd), and the stale "forces single-tick mode" help text
  removed (VCD capture uses a GPU ring buffer, preserving batched
  dispatch).
• netlist-graph cone no longer stops at driven internal nets and
  mislabels them [primary input] (#99). Inverting/tie output pins
  (ZN, LO, HI, QN, CO, …) were misclassified as cell inputs,
  so their output nets had no driver edge and looked undriven. The cone
  now follows them, and a genuinely undriven internal net is flagged
  [undriven — X-source] distinctly from a real top-level port; constant
  tie-cell outputs (sky130 conb_1) are labeled [constant: …].
• netlist-graph register detection (_is_register) now recognises
  reset/set/scan flop variants (sky130 dfrtp/dfstp/dfbbn/sdf*,
  gf180 dffrnq/latrnq), not just the plain DFF, by matching the
  functional cell name after the library prefix.

Deprecated / Removed

• ADR 0003 (OpenTimer as primary STA) superseded 2026-05-01
  (commit d002bde). OpenSTA-out-of-process is the sole STA path.
• src/sdf_parser.rs removed (WS3 phase 3.4); replaced by opensta-to-ir.

Documentation

• New: docs/release-process.md — lightweight release procedure.
• Updated: docs/why-jacquard.md — output-interface section now
  describes shipped surface; deferred items moved to "Still on the
  wishlist".
• Updated: docs/usage.md — § Timing-Aware Simulation describes
  --timing-ir vs --sdf paths plus OpenSTA version requirements.
• Updated: docs/timing-violations.md — new § Text Summary and
  § Structured JSON Report.
• Plan files: docs/plans/post-phase-0-roadmap.md tracks current
  workstreams; Phase 0 / Phase 1 closed.
• New: docs/bus-tracing.md and docs/signal-tracing.md — user guides
  for the two cosim observability features (decoded transactions vs. raw
  nets). ADR 0018 + docs/plans/distribution.md cover the install model.

Known limitations

• --timing-report and --timing-summary are wired only into the
  Metal sim path. The CUDA, HIP, and cosim paths detect violations on
  the GPU but do not yet route them through process_events. Tracked
  as a follow-up.
• The per-cycle violations array in --timing-report is capped at
  100k records by default (override via --timing-report-max-violations).
  Setup/hold totals + worst-slack always reflect every observed event;
  only the per-cycle list is bounded.
• worst_slack ranking is populated only from observed violation
  events. Closest-to-violation tracking on a run that passed timing
  needs GPU-side near-miss instrumentation; deferred.
• Bidirectional pads under --xprop resolve to conservative X when the
  output enable is deasserted; the precise tristate-mux read
  (Y = OE ? A : external) is deferred (#96).
• Timed output (sim --timed / cosim --output-vcd with timing data)
  routes violations through process_events only on the Metal sim path.
  CUDA / HIP detect violations on the GPU but don't currently route
  them; the JSON / text outputs only fire on Metal today.