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v0.2.0

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@robtaylor robtaylor released this 23 Jun 09:06
Immutable release. Only release title and notes can be modified.

Added

  • Interactive JTAG debug server (--jtag-server) (#124). jacquard cosim --jtag-server <PORT> opens a live remote_bitbang JTAG socket alongside the
    running GPU co-simulation, so an external debugger (OpenOCD, then gdb on top)
    can attach and drive the design's RISC-V Debug Module — halt/resume/step,
    read/write GPRs/CSRs/PC/memory, and load firmware — in lock-step with each
    debug transaction. The interactive sibling of --jtag-replay (recorded
    streams). Adds --jtag-reconnect (re-accept a debugger without restarting
    cosim) and a jacquard jtag-openocd-config helper that emits the matching
    openocd.cfg. Host-side only (no kernel changes); the CI gate is a real
    OpenOCD attach. See docs/jtag-debug.md.
  • reg_init register value-injection for cosim (#108). A new
    reg_init array in the testbench JSON deposits a definite value into
    chosen registers at tick 0 with $deposit semantics — the seed clears
    the power-up X-mask, then the design's own logic drives the register
    normally (NOT force, which would pin a CDC crossing register and write
    zeros across the handshake). Each entry is { "name", "value", "width" };
    a multi-bit register resolves name[0]..name[width-1] independently.
    This is the register sibling of sram_init and the fix path for
    X-poisoned unreset CDC launch registers (#102): depositing on the launch
    flops lets X-aware cosim of debug-loaded firmware proceed. Composes with
    the x-assert detection work (#106). Regression: tests/xprop_cosim/
    reg-init mode (cosim A/B — deposit clears the X that xprop mode
    requires to persist).

Fixed

  • cosim on SRAM-less designs no longer panics. A design with zero SRAM
    produced a nil MTLBuffer (new_buffer(0)) whose .contents() is null;
    the SRAM data buffer is now sized to max(1) word (matching the X-mask
    shadow buffer), so pure-logic designs run under jacquard cosim.
  • bi_24t bidirectional pad core read-back (#96). The AIG modelled a
    bidir pad's core read as Y = PAD always, so a design that drives a pad
    and reads it back in the same path read the external PAD net instead of
    its own drive A — wrong in two-state (reads the external stim/0) and
    conservatively-X under --xprop (the external pad is an undriven input).
    AIG::from_netlistdb now builds the tristate read-back combinationally as
    Y = OE ? A : external: on OE=1 the core reads its own drive A
    (X-exact — known whenever A is), on OE=0 it reads the external net.
    in_c/in_s input pads are unchanged. See ADR 0016. Unit test:
    aig::gf180mcu_chip_top_tests::bi_24t_models_tristate_readback.
  • Empty-partition flatten panic (#128). A partition with zero boomerang
    stages — which mt-kahypar can emit at high partition counts (finer
    partitioning or a large --num-blocks) — panicked in
    FlattenedScriptV1::from ("index out of bounds: len is 0"). Such partitions
    do no work and are now dropped before flattening.