Add synthesis rule variable for additional Yosys synth pass arguments

[magancarz]

This PR fixes a problem with technology mapping of adders which caused arithmetic operations such as addition or subtraction give incorrect results. It is caused by the abc command in the yosys synth pass before extracting and mapping fa/ha adders.

Steps to reproduce:

• Prerequisites:

  • Verilator (tested on commit 4990b441209)
  • asap7sc7p5t_28 and path to its base directory as env variable ASAP7_SOURCES (tested on commit f970bd3c32)
  • add_tb.sv, add.sv and BUILD.bazel design files added as attachments
  • it is assumed that design files will be placed in add as bazel_rules_hdl subdirectory

• Steps

  • Synthesize the design:

    bazel build //add:verilog_add_synth
    

  • Move the synthesized add module from the output directory to the design files and run verilation

    verilator --binary -Wno-TIMESCALEMOD --top-module add_tb add_tb.sv verilog_add_synth_synth_output.v \
        $ASAP7_SOURCES/Verilog/asap7sc7p5t_SEQ_RVT_TT_220101.v \
        $ASAP7_SOURCES/Verilog/asap7sc7p5t_SIMPLE_RVT_TT_201020.v \
        $ASAP7_SOURCES/Verilog/asap7sc7p5t_INVBUF_RVT_TT_201020.v \
        $ASAP7_SOURCES/Verilog/asap7sc7p5t_AO_RVT_TT_201020.v \
        $ASAP7_SOURCES/Verilog/asap7sc7p5t_OA_RVT_TT_201020.v
    

  • Simulate the design:

    ./obj_dir/Vadd_tb
    

• Output pre-change:

 10 +   3 =   0
 10 +   3 =  89
- add_tb.sv:18: Verilog $finish

• Output post-change:

 10 +   3 =   0
 10 +   3 =  13
- add_tb.sv:18: Verilog $finish

Design files:
add.zip

[mikesinouye]

/gcbrun

[magancarz]

Rebased PR changes onto latest main

[mikesinouye]

/gcbrun

[magancarz]

Updated the PR source in a way which now the -noabc flag can be added optionally while creating a rule for synthesis.

[mikesinouye]

/gcbrun