Skip to content

Add synthesis rule variable for additional Yosys synth pass arguments #410

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jul 17, 2025
Merged

Add synthesis rule variable for additional Yosys synth pass arguments #410

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 6 additions & 0 deletions synthesis/build_defs.bzl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -160,6 +160,7 @@ def _synthesize_design_impl(ctx):
"LIBERTY": default_liberty_file,
"OUTPUT": output_file,
"STANDARD_CELL_BLACK_BOX": standard_cell_black_box,
"SYNTH_ADDITIONAL_ARGS": ctx.attr.synth_additional_args,
"TOP": ctx.attr.top_module,
"UHDM_FLIST": uhdm_flist,
}
Expand Down Expand Up @@ -385,6 +386,11 @@ synthesize_rtl = rule(
providers = [StandardCellInfo],
default = "@com_google_skywater_pdk_sky130_fd_sc_hd//:sky130_fd_sc_hd",
),
"synth_additional_args": attr.string(
mandatory = False,
doc = "Additional args for the Yosys synth pass",
default = "",
),
"synth_tcl": attr.label(
default = Label("//synthesis:synth.tcl"),
allow_single_file = True,
Expand Down
8 changes: 7 additions & 1 deletion synthesis/synth.tcl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@
# OUTPUT = verilog file for synthesis output
# STATS_JSON = json file for structured stats output
# EARLY_TECHMAP = verilog/system verilog file for early techmap process
# SYNTH_ADDITIONAL_ARGS = Additional args for the Yosys synth pass

yosys -import

Expand Down Expand Up @@ -79,7 +80,12 @@ yosys delete {*/t:$print}
# pass.
yosys opt_clean -purge

yosys synth -top $top -noshare
set synth_args "-noshare"
if { [info exists ::env(SYNTH_ADDITIONAL_ARGS)] && ![string equal $::env(SYNTH_ADDITIONAL_ARGS) ""] } {
set synth_args "$synth_args $::env(SYNTH_ADDITIONAL_ARGS)"
}

yosys synth -top $top {*}$synth_args

# Remove internal only aliases for public nets and then give created instances
# useful names. At this stage it is all the other synthesizable constructs.
Expand Down