Helion v3.0.0

Helion 3.0.0

Original FPGA family + CAD. Native Apple Silicon app; Linux CLI tarball.
Unsigned macOS build — Gatekeeper will warn. Apache-2.0 OR MIT.

Two new product tracks plus a reliability sweep and a major IDE upgrade.

Added

• Xilinx 7-series backend (zero vendor tools, open bitstream databases only
  via Project X-Ray / prjxray):
  • New helion-backend crate: architecture-neutral Backend trait with
    associated stage types (Packed/Placed/Routed/Bitstream) and the
    pack to place to route to bitstream stage contract.
  • New helion-xilinx7 crate: xc7a35t device model (18,055 tiles), 7-series
    pack/place/route, human-readable FASM emission, frame resolution, and a
    .bit writer. Blinky runs end to end from SystemVerilog to a valid
    bitstream: FASM to frames is byte-identical against prjxray's
    fasm2frames.py, and the writer reproduces openXC7's blinky.bit
    byte-for-byte on identical frames.
  • helion-ir: new CellKind::IobIn (input IOB) and CellKind::ClockBuf
    (global clock buffer) with HNF round-trip support, plus a NetlistIr
    alias as the backend-neutral design input. HL10T pack now rejects these
    cells loudly instead of silently dropping them.
• Verification track:
  • SAT-based combinational equivalence checking (SolverBackend trait,
    varisat 0.2.1 backend, Tseitin encoding, LUT6 to AIG bridge, miter
    construction with counterexample reporting).
  • SVA subset: immediate assert, assert final, concurrent
    assert property, |->, |=>, fixed ##N, $rose/$fell/$stable,
    with parser, sim engine, and IDE integration (wave markers, Tcl
    assert_report).
  • CDC structural analysis in helion-sta: clock-domain extraction,
    crossing detection, synchronizer recognition, and all eleven violation
    classes with IDE integration (report_cdc_crossings, cross-probing).
    Handshakes and async FIFOs are flagged for review, never declared safe.
• Physical View 2.0: FPGA resource layers with solo/isolate controls,
  congestion and timing-criticality heat maps, inspector panel, find palette
  (Ctrl+K), ruler with tile and delay measurement, and upgraded die
  interaction (route hit-testing, multi-select, hover tooltips).
• UX pass 2: schematic level-of-detail for large designs (block rectangles
  with cell/port counts at fit zoom), hierarchy breadcrumb for large designs,
  waveform density toggle (Comfortable/Compact), scrolling tab bar and
  toolbar overflow menus, right-click context menus (timing rows, device
  canvas, waveforms), syntax highlighting in the sim source view, proper
  empty states, and a real clock-interaction matrix.

Fixed

• Stack overflow on deep priority chains: all recursive RExpr/Expr walkers on
  the synthesis path are now iterative with heap work stacks; the 50,000-deep
  regression test passes and debug Ibex synthesis no longer crashes.
• All 12 code-review criticals, each with a regression test: binary literal
  sizing, index_part small-value decoding, hierarchy cycle infinite
  recursion, mixed-width word-add carry drop, RExpr::Range lo/hi order,
  priority-grant heuristic scope, non-constant shift lowering (new
  RExpr::Shl), placer seed/site-index invariant, VCD truncation flag,
  generated-clock constraint target port, Tcl set_property KEEP, and Tcl
  string range out-of-range handling.

Gold: empty-XDC counter.sv WNS_PS=9640, LED[16]=0000000111111110.
Roadmap: https://github.com/helion-fpga/helion/blob/master/ROADMAP.md

Helion v2.5.0

Helion 2.5.0

Original FPGA family + CAD. Native Apple Silicon app; Linux CLI tarball.
Unsigned macOS build — Gatekeeper will warn. Apache-2.0 OR MIT.

Nine "best in the market" IDE features, toast/macOS hotfixes, and a UX fix batch.

Added

• Cross-probing: clicking a timing path lights it up in the device view and schematic (probe selection synced across views).
• Real Tcl console: inline console (bottom panel) plus a floating window on Cmd+Backtick; drives the same Session engines as the CLI, with expression syntax errors that report line numbers.
• Design runs + strategy sweep: named runs with strategy presets (Default, TimingExplore, RuntimeOpt, PhysOpt, Custom), per-run placer seed / router iters / AIG rewrite / timing-driven / phys-opt toggles, queue with streaming results, seed sweeps, and best-run activation.
• Checkpoints: save/restore named implementation checkpoints; checkpoint manager pane.
• Integrated testbench runner: discover *_tb.sv testbenches, run them against the sim kernel (full net resolution for LUT pins, driven top-level inputs, multi-level LUT chains), stream logs with severity coloring.
• Constraints wizard: visual SDC editor — clocks, I/O delays, false paths, and multicycle exceptions with a draft/apply flow.
• QoR suggestions engine: analyzes the implemented design and surfaces prioritized, actionable QoR suggestions with severity levels.
• VCD-driven power estimation: VCD dumper with exact multi-level LUT-chain net resolution, switching-activity power report with severity-graded nets.
• ILA / logic analyzer: sim-side ILA with probe selection, edge/value triggers, waveform viewer (GTKWave-style with cursor/A-B markers), and VCD export marking invalid samples as X.
• Editable source editor (UX batch): click-and-type editing with syntax highlighting, VS Code-style minimap, line numbers, dirty indicator, Cmd+S save, Alt+Z soft-wrap.

Fixed

• Toast notifications no longer pile up as giant permanent cards: they auto-dismiss after 5s on a wall-clock timer (the old frame-count timer never expired while the UI was idle), are capped at 360px with wrapping, max 4 stacked, deduped, and the "Started: …" spam is gone — job progress already lives in the status bar; toasts are completions/errors only.
• macOS: ad-hoc codesign the Helion.app bundle during the release build (and verify it in CI). Unsigned downloads were reported as "damaged" by Gatekeeper on recent macOS; the bundle is now well-formed. The bundle version is stamped from workspace.package.version at build time (no more hardcoded plist version). First launch from a download still needs one xattr -cr /Applications/Helion.app (documented in the README) until Apple notarization is set up.
• UX audit fixes: red Timing warnings resolved, bottom panel holds its drag position, the Tcl tab no longer pops a floating dialog (inline console under the "Console" tab instead), toolbar scrolls on narrow windows, console opens with a clean "session started" separator.

Gold: empty-XDC counter.sv WNS_PS=9640, LED[16]=0000000111111110.
Roadmap: https://github.com/helion-fpga/helion/blob/master/ROADMAP.md

Helion v2.1.0

Helion 2.1.0

Original FPGA family + CAD. Native Apple Silicon app; Linux CLI tarball.
Unsigned macOS build — Gatekeeper will warn. Apache-2.0 OR MIT.

Performance campaign, area campaign, and IDE rebuild.

Added

• Permanent criterion benchmark harness for all five engines (synth, pack, place, route, STA), a full-flow profiler, and a perf-budget proposal.
• ABC-style AIG rewriting in synthesis: structural hashing, K=4 cut enumeration, exact minimum-AND truth-table resynthesis, and cross-cone structural sharing via one global hashed AIG — all guarded by exhaustive miter equivalence tests.
• IDE: rebuilt Project Summary (8 space-filling sections), real code editor (line-number gutter, syntax highlighting, breadcrumbs, diagnostic gutter ticks, CJK font fallback), expandable hierarchy tree, schematic level-of-detail (hierarchical block treemap at fit zoom, gate sheet on zoom-in), sortable timing tables with endpoint-slack histogram, clickable status bar.
• 80-surface screenshot gallery (helion-research/surfaces/) covering PicoRV32 and Ibex across all 28 workspace tabs.
• README overhaul with hero screenshots, measured benchmarks, and architecture/roadmap docs.

Changed

• Synthesis frontend allocations 12.7M → 409k (−97%); frontend wall time −69% (arena-allocated elaboration, borrowed tokenizer spans, arena parser, interned names).
• Area: uart 420 → 244 LUTs (−42%), spi 73 → 52 (−29%), cnt16 37 → 16 (−57%), cmp16 39 → 20 (−49%); PicoRV32 −19% LUTs from AIG rewriting and −10% further from cross-cone sharing (63% of cross-cone logic was structurally duplicated).
• Rtl/RExpr now borrow &str name spans and arena-allocate nodes instead of per-node String/Box.

Fixed

• Unpacked-word output IOBs were attached to undriven net names while the real output nets went nowhere.
• 16-bit counters silently dropped bit 15.
• Cross-cone sharing polarity corruption (an output node reused inside another cone's logic) — caught by new multi-cone miter tests before shipping.
• DRC message column clipped at 1600px; Timing Constraints button now shows the actual filename.
• Ibex CJK comments rendered as ????? (bundled font lacked CJK glyphs; DroidSansFallback wired as fallback).

Gold: empty-XDC counter.sv WNS_PS=9640, LED[16]=0000000111111110.
Roadmap: https://github.com/helion-fpga/helion/blob/master/ROADMAP.md

Helion v2.0.5

Helion 2.0.5

Original FPGA family + CAD. Native Apple Silicon app; Linux CLI tarball.
Unsigned macOS build — Gatekeeper will warn. Apache-2.0 OR MIT.

School-schedule catch-up release with critical PNR, DRC, GUI, and SV fixes.
Note from maintainer: Updates have been slightly delayed recently due to demanding school commitments.

Changed

• Scaled Pathfinder A* heuristic by HOP_DELAY_PS (40 ps) in helion-route, preventing search degradation into unguided Dijkstra exploration.
• Pre-indexed driver nets into a HashSet in helion-drc for ROUTE-3, reducing check complexity from O(I×N) to O(I+N).
• Added 50ms polling backoff to GUI background task receiver (TryRecvError::Empty), eliminating 100% CPU core busy-spinning during CAD runs.
• Historical baseline: 9b864af all 272485 B dense bitstream.

Fixed

• Fixed dead stores in crates/helion-route/src/lib.rs (overused, last_paths).
• Restored missing #[test] attributes on 3 dead tests in crates/helion-sv/src/lib.rs (bufif1_mux_is_one_gate_primitive_not_a_lut, clock_mux_posedge_is_not_a_user_clock, string_param_width_does_not_panic).
• Resolved QoR test assertions in crates/helion-cli/tests/qor.rs by adding semantic markdown table column parsing.
• Fixed unused mutability and deprecated SelectableLabel compiler warnings across helion-sv, helion-gui, helion-vhdl, and helion-lab.

Gold: empty-XDC counter.sv WNS_PS=9640, LED[16]=0000000111111110.
Roadmap: https://github.com/helion-fpga/helion/blob/master/ROADMAP.md

Helion v2.0.4

Helion 2.0.4

Original FPGA family + CAD. Native Apple Silicon app; Linux CLI tarball.
Unsigned macOS build — Gatekeeper will warn. Apache-2.0 OR MIT.

OPT P1-2 STA HashSet (#62), P1-3 bitgen frame buffer (#63), place-legalize
(#64), residual synth_rtl (#65), residual parse (#66). Empty-XDC
examples/counter.sv gold unchanged (WNS_PS=9640). SOFT ≠ PASS held.
Release helion impl examples/ibex_pin_wrap.sv: parse 416→353 ms,
synth_rtl 670→524 ms, place legalize 213→23 ms, imux_skip 158→123.
Native Apple Silicon Helion.app ships on this GitHub Release.

Changed

• report_timing_placed uses a HashSet of IOB from_net (O(1) membership;
  kills O(lutffs×iobs)).
• Bitgen writes through a frame buffer (no .hbits format growth).
• Place legalize: dense occupancy grid, remaining-illegal worklist, pin-index
  scoring, high-fanout driver sampling.
• synth_rtl: single-pass emit_module_into; process-level OwnCache; no Rtl
  clone before synth.
• Parse: process-level SyntaxTree Arc cache (OnceLock+Mutex).

Fixed

• Ibex pin-wrap wall after #64/#65/#66: legalize −89%, synth_rtl −22%,
  parse −15% vs post-#64 / post-#65 baselines. Diagnostic depth unchanged.

Gold: empty-XDC counter.sv WNS_PS=9640, LED[16]=0000000111111110.
Roadmap: https://github.com/helion-fpga/helion/blob/master/ROADMAP.md

Helion v2.0.3

Helion 2.0.3

Original FPGA family + CAD. Native Apple Silicon app; Linux CLI tarball.
Unsigned macOS build — Gatekeeper will warn. Apache-2.0 OR MIT.

OPT P0-2 stitch/cache + P0-3 parse preprocess (wip/opt-sv-wall / #60). Empty-XDC
examples/counter.sv gold unchanged (WNS_PS=9640). SOFT ≠ PASS held. On
release helion impl examples/ibex_pin_wrap.sv after rebase: parse ~347 ms,
synth_rtl ~644 ms (cells=16756 luts=11572). Native Apple Silicon Helion.app
ships on this GitHub Release.

Changed

• OwnCache holds Arc<Design>; hierarchy stitch appends cells with a port
  HashMap (no 13k-cell clone per wrapper); assign_cap / early LUT6 before
  expr_node_count. No AIG/flowmap rewrite.
• Parse: byte preprocess (no Vec<char>), leftover-backtick pass; path+mtime
  SyntaxTree cache (thread-local Arc).

Fixed

• Ibex pin-wrap wall: synth_rtl first-run cut ~16% vs pre-opt scout pair;
  parse ms down. Diagnostic depth unchanged.

Gold: empty-XDC counter.sv WNS_PS=9640, LED[16]=0000000111111110.
Roadmap: https://github.com/helion-fpga/helion/blob/master/ROADMAP.md

Helion v2.0.2

Helion 2.0.2

Original FPGA family + CAD. Native Apple Silicon app; Linux CLI tarball.
Unsigned macOS build — Gatekeeper will warn. Apache-2.0 OR MIT.

Learner L1–L4 surfaces + OPT P2-1 / P0-1 / P1-1. Empty-XDC examples/counter.sv
gold matches helion qor: WNS_PS=9640, LUTFF=4, IOB=1, BYTES=185. Native
Apple Silicon Helion.app ships on this GitHub Release.

Added

• SoftDiag / MapResult IR schema (L3); VHDL emit into MapResult.softs (no
  parallel table). SOFT ≠ PASS.
• L2 HAD stable Site/BEL/PIP/Net IDs; PNR highlight set + GUI HighlightSet /
  packing wire-up (L2-UI).
• L1 GUI status rail provenance; L4 overlay sim_DONE + stable
  HELION_E_EMPTY_BITSTREAM / HELION_E_USB_0 refuse codes.

Changed

• Cap/QA scripts prefer release helion when present (OPT P2-1).

Fixed

• Budgeted IMUX legalize under affinity_cap (OPT P0-1).
• PathFinder A* buffer reuse, denser congestion, IOB→lutff index (OPT P1-1).
• Multi-IOB path delay / highlight indexing in STA/route (L2-PNR).

Gold: empty-XDC counter.sv WNS_PS=9640, LED[16]=0000000111111110.
Roadmap: https://github.com/helion-fpga/helion/blob/master/ROADMAP.md

Helion v2.0.1

Helion 2.0.1

Original FPGA family + CAD. Native Apple Silicon app; Linux CLI tarball.
Unsigned macOS build — Gatekeeper will warn. Apache-2.0 OR MIT.

Soft-clear polish on the 2.0.0 bar. Empty-XDC examples/counter.sv gold is
unchanged (WNS_PS=9640). Native Apple Silicon Helion.app ships on this
GitHub Release.

Fixed

• generate_not_lowered prim_ram_1p_scr; hierarchical outstanding_*/RVFI
  assigns. cells 17027→16741, luts 11845→11559. fcov_ not invented.

Gold: empty-XDC counter.sv WNS_PS=9640, LED[16]=0000000111111110.
Roadmap: https://github.com/helion-fpga/helion/blob/master/ROADMAP.md

Helion v2.0.0

Helion 2.0.0

Original FPGA family + CAD. Native Apple Silicon app; Linux CLI tarball.
Unsigned macOS build — Gatekeeper will warn. Apache-2.0 OR MIT.

Public OSS CAD bar. A stranger can clone, cargo test --workspace (helion-gui
lib green), run headless gold WNS_PS=9640, and trust the legal fence.
Native Apple Silicon Helion.app ships on this GitHub Release.

Added

• Disk .hckp CLI ECO path (read_checkpoint alias; open → ECO → bitstream
  hash change).
• IDE clock/led-optional contract (VHDL keep-name; HFF add_wave).
• Soft-clear track: Ibex wide_cone / if_stage generate / assign batches /
  rvfi+icache generate lowering with named leftovers (SOFT ≠ PASS).

Fixed

• helion-gui lib: 189 passed (was 14 failing on timing panes, UG900, Zoom Fit,
  scopes, expand_inside).
• Lab honesty: empty refuse; no-cable refuse DONE; overlay labeled.
• PNR issue #16 closed (timing_weight moves closed WNS).

Legal fence (unchanged)

Original Helion ISA/CAD only. No Project X-Ray, UNISIM, vendor Tcl product
names, or AMD/Intel/Lattice backends. Helion-MM / Helion-ST only.

Gold: empty-XDC counter.sv WNS_PS=9640, LED[16]=0000000111111110.
Roadmap: https://github.com/helion-fpga/helion/blob/master/ROADMAP.md

Helion v1.6.0

Helion 1.6.0

Original FPGA family + CAD. Native Apple Silicon app; Linux CLI tarball.
Unsigned macOS build — Gatekeeper will warn. Apache-2.0 OR MIT.

IDE clock/led contract + disk .hckp CLI ECO. Empty-XDC examples/counter.sv
gold is unchanged (WNS_PS=9640). Native Apple Silicon Helion.app ships on
this GitHub Release.

Added

• CLI open.hckp → ECO LUT → write_bitstream hash change; read_checkpoint
  alias for restore.
• VHDL clock port keep-name so GUI HFF / add_wave contract holds on rng/blinky.

Fixed

• Lab honesty already on master (empty refuse / no-cable refuse DONE / overlay
  labeled). Issue #16 PNR closed-WNS closed.

Gold: empty-XDC counter.sv WNS_PS=9640, LED[16]=0000000111111110.
Roadmap: https://github.com/helion-fpga/helion/blob/master/ROADMAP.md