Shield Revisions
Maximum VPP is 13 V on every revision. All revisions carry 20 address lines.
| Revision | Jumper | Detection | Notes |
|---|---|---|---|
| Rev 0 | — | No version resistor. A3 floats; A2 has no divider. | 32-pin chips above 64 KB get the un-dropped VPE rail on pin 1 instead of the dropped 13 V — A16 and the VPP drop share one control bit. Cannot read VPP back at all, so VPP is never verified. |
| Rev 1 | — | No version resistor. A3 floats; A2 divider reads below 1000. | 32-pin chips above 64 KB get the un-dropped VPE rail on pin 1 instead of the dropped 13 V — A16 and the VPP drop share one control bit. |
| Rev 2.0 | JP4, 1×2 | R41 = 4.7 kΩ on A3. | |
| Rev 2.1 | JP4, 1×2 | R41 = 4.7 kΩ on A3. | |
| Rev 2.2 | JP4, 1×3 | R41 = 10 kΩ on A3. | JP4's third position reroutes VPP, which is what reaches the TI 2516 and 2532. Both take 25 V. |
| Rev 2.3 | JP4, 1×3 | R41 = 10 kΩ on A3. | JP4's third position reroutes VPP, which is what reaches the TI 2516 and 2532. Both take 25 V. |
JP4 is the VPP bypass jumper.
On Rev 0 and Rev 1 the 32-pin part is programmed on the un-dropped VPE rail
instead, which sits above the intended 13 V. It reaches any 32-pin part above
64 KB, since A16 is asserted from address 65536 upward — 126 chips on protocol
0x08. On Rev 2 boards the drop and A16 are separate control bits and do not
interact.
A3 is sampled at boot, 8-sample average:
| A3 reading | Result |
|---|---|
| below 200 | Rev 2.0 |
| 200 – 219 | unknown |
| 220 – 599 | Rev 2.3 |
| 600 and above | A2 below 1000 → Rev 1, otherwise Rev 0 |
Rev 2.0, Rev 2.1 and Rev 2.2 share the low band and all report as Rev 2.0. Set
the revision explicitly with firestarter rev <N> to distinguish them.
Control-register bit assignments differ between the Rev 1 and Rev 2 generations — see Pin Maps.
Relocated from firestarter/doc/SHIELD-REVISIONS.md in firestarter at a218b4f5273d14f0abd796b21ac104792de01603, then trimmed 2026-08-31 on the wiki; not re-verified against the code.