Panelization Issue

[sam-1647]

Hi,

I have previously used the Penalization using "Manage Included Boards" & "Place Board Panel" tools in PCB editor without an issue.
Recently I created a panel in v2.7.2 and ran into problem.

As you can see from image above, there are 2 different designs in the panel with same size and shape.
But upper board shows strange artifacts of Blank Spaces, from on Copper Layers from Lower Board. This happens in both Top and Bottom Copper layers. It also gets shown in 3rd PCB(same as second copy of upper PCB or entirely different design), if I add it to panel.

Fortunately, the gerbers & drill files generated from panel, are okay as far as I am able to check.
Still visual issue is quite problematic.

_sam

[carrotIndustries]

That does indeed look like a bug. Do you have a minimum working example you can share to reproduce this issue?