feat/linear scan register allocator#376
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nahime0
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Jun 16, 2026
nahime0
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- docs: rewrite eir-06 plan for full linear-scan register allocator
- feat(ir_passes): implement liveness analysis for EIR functions
- feat(ir_passes): build linear-order live intervals from liveness
- feat(ir_passes): linear-scan allocator core with int/float pools and spilling
- feat(codegen_ir): wire linear-scan allocator into EIR backend behind --regalloc
- docs: document linear-scan register allocation in the-ir.md
- fix(ir_passes): restrict x86_64 allocation pool to rbx
- docs: mark linear-scan register allocator complete in ROADMAP
…--regalloc Default to the linear-scan register allocator with callee-saved preservation; --regalloc=stack (or ELEPHC_REGALLOC=stack) selects the spill-everything fallback. Value-access chokepoints become allocation-aware, prologue/epilogue save and restore used callee-saved registers, and emit_reg_move handles GP<->FP moves. Full codegen suite passes under both modes on macOS aarch64.
r14/r15 are used as scratch by hand-written x86_64 runtime routines and shared heap-marker codegen without ABI-compliant save/restore, so values held there across calls get corrupted (observed as heap exhaustion in spread/variadic tests). Only rbx is reliably preserved. Full codegen suite now passes on Linux x86_64, Linux aarch64, and macOS aarch64.
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