v0.0.8

Highlights

• Run AReno natively on Apple Silicon with the new MLX training and OpenAI-compatible serving backend, while retaining CUDA as the Linux backend (#493).
• Train and serve standard PEFT-compatible LoRA adapters: CUDA supports Qwen3, Qwen3-MoE, and supported Bailing-MoE V3 checkpoints, and MLX supports unquantized Qwen3 Dense text checkpoints (#488, #552).
• Expand multimodal support with Gemma 4 and MiniCPM-V 4.6 serving, training, reinforcement learning, and checkpoint workflows (#455, #479, #505).
• Reduce optimizer memory with opt-in packed 4-bit AdamW states and dynamic 8-bit state routing across CUDA and MLX (#537, #543).

Features

• Add an integrated MLX backend for Apple Silicon covering SFT, DPO, GRPO, GSPO, PPO, continuous-batch serving, native checkpoints, and supported multimodal models (#493).
• Add end-to-end MLX LoRA training, PEFT adapter import/export, adapter-only checkpoints, reload, and serving for supported Qwen3 Dense models (#552).
• Add tensor-parallel native LoRA training and serving for Qwen3, Qwen3-MoE, and supported Bailing-MoE V3 models on CUDA (#488).
• Add Gemma 4 image, audio, and video serving and agentic multimodal training, together with an AVE event-recognition example (#479).
• Add MiniCPM-V 4.6 image-to-text serving and training, followed by configurable vision-tower/projector optimization, policy synchronization, and complete checkpoint round trips (#455, #505).
• Add opt-in packed 4-bit AdamW optimizer states and block-wise dynamic AdamW8bit state routing, including mixed-precision state handling and checkpoint support (#537, #543).
• Add rollout routing replay for CUDA sparse-MoE reinforcement learning to reduce rollout/training expert-selection drift (#524).
• Add activation checkpointing for Ling/Bailing V3 attention, dense MLP, and sparse expert execution (#540).
• Add a terminal-hacking agentic reinforcement-learning demo and browser UI (#529).

Fixes

• Correct OpenAI-compatible serving usage accounting so prompt tokens are counted once (#460).
• Fix Bailing/Ling tensor-parallel gradient reduction, recurrent-cache slot isolation and reuse, recurrent-slot reset behavior, and log-probability metric aggregation (#496, #499, #500, #520).
• Preserve structured special tokens during rollout and lazily register bundled model-family adapters (#477, #502).
• Reuse inference state safely across agentic turns and isolate recurrent CUDA Graph scratch state (#507, #509).
• Correct packed sequence-parallel training across supported models (#510).
• Avoid CUDA optimizer hangs and non-disk slowdowns, preserve disk-offloaded gradient paths, and release CUDA cache after each training step (#512, #513, #515).
• Allocate distributed initialization ports outside the ephemeral range (#518).
• Remove the rollout proxy request timeout for long-running agentic workloads (#530).
• Keep oversized rollout batches pending instead of dropping them (#539).

Performance and maintenance

• Reduce FP32-master AdamW peak memory (#498).
• Reduce CPU-side materialization overhead in the policy-only trainer and vectorize train-pack construction (#508, #516).
• Add native-attention GPU equivalence coverage (#473).
• Align repository skill-count checks with the current skill inventory (#549).
• Add notes from the August 21, 2026 community meeting (#519).
• Bump the package and container version to v0.0.8.

Upgrade notes

• Dependencies are now platform-specific: Linux installs the PyTorch/CUDA stack, while native Apple Silicon installs MLX, MLX-LM, and MLX-VLM. Unsupported platforms fail explicitly instead of falling back to another backend.
• The supported Transformers range is now >=5.15,<6.
• MLX runs with --world-size 1 --tp-size 1. MLX LoRA currently requires an unquantized Qwen3 Dense text checkpoint, zero LoRA dropout, and an independent reference model; QLoRA, Qwen3-MoE, multimodal LoRA, and multiple adapters are not supported on MLX in this release.
• LoRA checkpoints are adapter-only PEFT artifacts. Continue to provide the original base checkpoint when training or serving; optimizer, scheduler, RNG, and trainer cursor state are not included for exact resume.
• AdamW8bit optimizer checkpoints created by the previous linear-state implementation are not supported by the new dynamic block-wise implementation.

Full Changelog: v0.0.7...v0.0.8