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Sync/apx 20260806 - #588

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hongyuni merged 2 commits into
intel:mainfrom
hongyuni:sync/apx-20260806
Aug 6, 2026
Merged

Sync/apx 20260806#588
hongyuni merged 2 commits into
intel:mainfrom
hongyuni:sync/apx-20260806

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@hongyuni hongyuni commented Aug 6, 2026

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xhao22 added 2 commits August 6, 2026 10:53
Add test suite for Intel APX (Advanced Performance Extensions) covering:

CPUID enumeration (4 tests):
  - Feature bit, XSAVE/OSXSAVE, XCR0[19], XSAVE area size/offset

XSAVE state component 19 (5 tests):
  - State size/offset validation, signal/fork/context-switch preservation

Direct EGPR access (3 tests):
  - Individual R16-R31 read/write, simultaneous 16-register load, syscall

APX instruction encodings (13 tests):
  - NDD (add/sub/and/or/xor/shl/shr), NF (add/sub/inc/dec),
    CFCMOV, PUSH2/POP2

Signed-off-by: Xudong Hao <xudong.hao@intel.com>
(cherry picked from commit 305e4e4)
… tests

These tests exercise __copy_xstate_to_uabi_buf() and
copy_uabi_to_xstate() kernel paths modified by the APX commit series.

apx_ptrace (3 tests):
  - ptrace_get: PTRACE_GETREGSET reads EGPR via NT_X86_XSTATE
  - ptrace_inject: SETREGSET + GETREGSET roundtrip verification
  - ptrace_modify: Individual EGPR value injection and readback

apx_sigcontext (5 tests):
  - sigctx_magic: FP_XSTATE_MAGIC1/MAGIC2 presence in signal frame
  - sigctx_xfeatures: fpx_sw_bytes.xfeatures includes APX bit
  - sigctx_xstatebv: XSTATE_BV in XSAVE header includes APX bit
  - sigctx_delivery: EGPR data correctly delivered in signal frame
  - sigctx_restore: Modified EGPRs in handler persist after sigreturn

apx_ctxsw (1 test):
  - ctxsw_threads: 5-thread mutex-handoff on single CPU with
    randomized EGPR values, verifying state survives context switches

Signed-off-by: Xudong Hao <xudong.hao@intel.com>
(cherry picked from commit 6b79554)
@hongyuni
hongyuni merged commit 2953049 into intel:main Aug 6, 2026
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2 participants