Collapse adjacent bit selects in swizzles to ranges

[mkorbel1]

Description & Motivation

This improves generated SystemVerilog for swizzles by compacting descending contiguous single-bit selections into legal slice expressions.

Examples:

• {a[7], a[6], a[5]} can now emit as a[7:5]
• {arr[0][1], arr[0][0]} can now emit as arr[0][1:0]

The collapse is intentionally conservative. It only applies to descending contiguous bit selects from the same packed source, and leaves unsupported cases expanded, including ascending selections, adjacent pre-existing range operands, expression-based selects, nested swizzle boundaries, and unpacked array sources.

Related Issue(s)

N/A

Testing

Added new tests, updated some other tests

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

No

[desmonddak]

I think this PR makes sense right now to get SV much cleaner. I could see pushing some of the optimizations into the base and leaving here some SV-specific conventions like [:7]. Otherwise, the collapse could be structural, and then the strings would come out from there unless we are avoiding structural change in the synth layer for this case.

[mkorbel1]

I agree, makes SV a lot cleaner and is pretty elegant and limited, we can look for additional opportunities for reuse when the situation actually presents itself