Restore SystemVerilog port defaults and add per-direction type configuration

[mkorbel1]

Description & Motivation

The explicit/implicit port type configuration added in #678 changed the default generated SystemVerilog from ROHD's historical port declarations:

• input logic
• output logic
• inout wire

to fully explicit declarations:

• input wire logic
• output var logic
• inout wire logic

This caused compatibility issues in some downstream flows. It also exposed a limitation in the original configuration: a single object/data type policy cannot represent the historical defaults because inout ports require different settings from input and output ports.

This PR restores the historical generated declarations by default and makes object and data type emission independently configurable for each port direction.

• Adds SystemVerilogPortTypeConfiguration for controlling object and data type emission together.
• Adds separate inputPortType, outputPortType, and inOutPortType settings to SystemVerilogSynthesizerConfiguration.
• Restores the default generated declarations to:
  • input logic
  • output logic
  • inout wire
• Supports independently configuring explicit or implicit object and data types for each port direction.
• Updates generated-SystemVerilog expectations throughout the test suite.
• Updates the generation documentation and changelog.

Related Issue(s)

#678

Testing

Added new tests

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No (previous PR changes are not released yet)

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

Yes, included