v1.91

What's Changed

• SMU: add Carrizo and Stoney Ridge codenames, improved pre-Ryzen support by @Erruar in #26
• mock: parse report version, core count and per-module timings by @deadfellow34 in #27
• Add APOB support for dynamically discovering block layouts and field offsets
• Add APOB parsing for CCDL, CCDL-WR and CCDL-WR2 values
• Add Zen 5 APOB DRAM impedance/termination parameters
• Add support for additional Strix Point and Strix Halo PMT table versions
• Add PMT fields for additional voltage/power telemetry
• Add AGESA version detection through the SMBIOS firmware table
• Extend SVI3 voltage readings from PMT (renamed from SMU and adjusted offsets) for newer Zen 4/Zen 5 platforms
• Extend DDR5 SPD/PMIC support for newer DIMM and PMIC configurations
• Fix DRAM impedance decoding for values outside the standard dictionary range
• Fix PMT refresh handling when another application has already initialized the table
• Improve MMIO register discovery across Zen generations

New Contributors

• @deadfellow34 made their first contribution in #27

Full Changelog: v1.90...v1.91