v0.1.1
What's Changed
- chore: remove unused cpu-logo.png (#55)
- docs: use social preview banner as README header image (#53)
- docs: add Zenodo DOI to CITATION.cff and README (#51)
- fix(ci): repair changelog workflow and promote CHANGELOG to 0.1.0 (#49)
🔄 Changed
- refactor(isa): introduce ISA-agnostic core (RISC-V groundwork) (#57)
📖 Documentation
- docs(wiki): document ISA-agnostic core split and RISC-V roadmap (#59)
This release is internal groundwork: it carves the ISA-agnostic isa:: core out of
the MIPS backend so a RISC-V (RV32I) backend can reuse the memory, register file,
pipeline state, and processor interface. No user-facing behavior change.
Full Changelog: v0.1.0...v0.1.1